Random Work-Function-Induced Threshold Voltage Fluctuation in Metal-Gate MOS Devices by Monte Carlo Simulation

Li, Yiming; Cheng, Hui-Wen

doi:10.1109/tsm.2011.2181964

Cited by 18 publications

(9 citation statements)

References 13 publications

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“…The overall shape of the grains in Fig. 1(b) is similar to what was shown in [2] where the grains in a metal gate are partitioned into several square-shaped sub-regions in order to simply estimate the WFV. In fact, the overall shape of the grains shown in Fig.…”

Section: Introductionmentioning

confidence: 54%

“…Several studies for estimating random parametric failures caused by LER/LWR and RDF have been performed. A few studies on WFV modeling, however, have been performed [1,2], and an experimental study on WFV has been demonstrated [3]. In this study, a Monte Carlo (MC) simulation is used to generate arbitrary grain sizes by following two different probability distributions (ie, Gaussian and Rayleigh distributions) in a given limited gate area of a high-k/metal-gate (HK/MG) device in order to improve the physical validity of the model (section 2).…”

Section: Introductionmentioning

confidence: 99%

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Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size

Nam

Shin

2013

IEICE Electron. Express

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Because of the significantly-increasing work-function variation (WFV) in high-k/metal-gate technology in sub-30-nm nodes, a simple but reasonable model for quantitatively estimating the WFV is currently required. In this study, a Monte Carlo simulation for statistically generating the grain sizes following two different probability distributions (ie Gaussian and Rayleigh distributions) is suggested and performed. The shapes of the grains created by following the Rayleigh distribution (vs the Gaussian distribution) are significantly closer to the real shapes of the grains in the metal gate of TiN. Thus, the WFV estimated by using the Rayleigh distribution is well matched to the previous results.

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Section: Introductionmentioning

confidence: 54%

Section: Introductionmentioning

confidence: 99%

Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size

Nam

Shin

2013

IEICE Electron. Express

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“…In order to realize the adequate device scaling, various new materials have been introduced in the MOSFETs [1][2][3][4][5][6] especially for the gate stack structures [7][8][9][10][11]. With the device scaling, ultrathin gate insulator is necessary to be introduced.…”

Section: Introductionmentioning

confidence: 99%

Variability Improvement by Si Surface Flattening of Electrical Characteristics in MOSFETs With High-k HfON Gate Insulator

Ohmi

Kudoh

Atthi

2015

IEEE Trans. Semicond. Manufact.

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Variability improvement of metal-oxidesemiconductor field-effect transistors (MOSFETs) characteristics with high-k HfON gate insulator by Si surface flattening was investigated. The Si surface flattening process was carried out by Ar/4.9%H2 anneal utilizing rapid thermal annealing (RTA) system. The HfON gate insulator was formed by the in-situ Ar/O2 plasma oxidation of HfN utilizing electron cyclotron resonance (ECR) plasma sputtering followed by the post deposition anneal (PDA) at 600 o C for 1 min. The Si surface flattening was found to significantly improve the threshold voltage variability (VTH) of MOSFET with HfON gate insulator for the first time. Furthermore, the stability of the device characteristics was improved up to the measurement temperature of 100 o C by introducing the Si surface flattening process. Index Terms-ECR plasma sputtering, gate insulator, HfON, high-k, MOSFETs, Si surface flattening, variability 0894-6507 (c)

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“…Devices with high-κ/metal-gate (HKMG) [1][2] and strained technologies [3][4] are important not only for nowadays planar metal-oxide-semiconductor field effect transistor (MOSFET) devices but also for advanced bulk FinFET devices. Devices with HKMG stacks can reduce the gate leakage; and, the source/drain (S/D) epi growth will boost device performance; however, characteristic fluctuations resulting from process variation effects and random effects [5][6][7] complicate process development of the 16-nm devices.…”

Section: Introductionmentioning

confidence: 99%

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

2015

IEEE Trans. Semicond. Manufact.

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Effective extraction of source/drain (S/D) series resistances is a challenging task owing to poor epi-growth and non-uniform distribution of current density in S/D, critical limitation of restrictive design rule, ultra-thin contact film, and complicated 3D FinFET structure. In this paper, we report a test structure for measurement of linear and non-linear S/D series resistances. This technique enables us to evaluate each component of S/D series resistances resulting from the S/D contact, the S/D epi-growth fin, the S/D extension, and the channel gate, respectively. The S/D series resistance for fins on different layout location of the same diffusion is characterized and modeled by connection with a specified S/D contact on it. Furthermore, the S/D series resistance of each fin can be analytically calculated, respectively, by swapping the S/D bias condition. The proposed test structure and extraction technique provides a robust monitoring tool to diagnose a process weak point of the 16-nm multi-fin high-κ/metal gate bulk FinFET devices.

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Random Work-Function-Induced Threshold Voltage Fluctuation in Metal-Gate MOS Devices by Monte Carlo Simulation

Cited by 18 publications

References 13 publications

Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size

Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size

Variability Improvement by Si Surface Flattening of Electrical Characteristics in MOSFETs With High-k HfON Gate Insulator

Source/Drain Series Resistance Extraction in HKMG Multifin Bulk FinFET Devices

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