Asynchronous Sequential Switching Circuits

Unger, Stephen H.; Su, Stephen Y. H.

doi:10.1109/tsmc.1973.4309232

Cited by 246 publications

(178 citation statements)

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“…Furthermore, a quantum operation cannot be applied to a QBC unless the previous one is complete and the quantum system is stable. This behavior is similar to the fundamental mode of asynchronous circuits [9,10,16].…”

Section: Self-timed Systemssupporting

confidence: 66%

“…Because the operations of a quantum Boolean circuit are similar to asynchronous circuit behaviors in the fundamental mode [9,16], we exploit the specifications of asynchronous circuit design to construct sequential quantum Boolean circuits. Note that asynchronous circuits can also operate in input-output mode.…”

Section: Self-timed Systemsmentioning

confidence: 99%

“…2(b) is reversible since the indegree of all nodes in USCRSG is equal to one. Figure 4 illustrates an irreversible SG which is the circuit specification of a call module [16]. This SG cannot be synthesized since node 10 has two source nodes, node 7 and node 8 and ob(node 7 ob(node 8).…”

Section: Perform Reversible Checking and Unique State Encodingmentioning

confidence: 99%

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Automatic synthesis of composable sequential quantum Boolean circuits

Chang

Cheng

2005 International Conference on Computer Design

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Section: Self-timed Systemssupporting

confidence: 66%

Section: Self-timed Systemsmentioning

confidence: 99%

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Automatic synthesis of composable sequential quantum Boolean circuits

Chang

Cheng

2005 International Conference on Computer Design

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“…[7] The above encoding constraints can be described using dichotomies [1,14]. Given a set of states S, a dichotomy is a bipartition (U V ) of a subset T of states of S. In a given state assignment, a binary state variable yi covers the dichotomy (U V ) if yi = 0 for every state in U and yi = 1 for every state in V (or vice-versa) [15,14]. For the given problem, a set of n-to-1 dichotomies is formed, i.e., between each state group Sp (containing n states) and each single disjoint state s 6 2 Sp.…”

Section: Optimal State Assignment For Synchronous Machinesmentioning

confidence: 99%

“…These methods have been automated and produce low-latency machines which are guaranteed hazard-free at the gate-level. The design tools have benefited from a number of hazard-free optimization algorithms: exact two-level logic minimization [10], multi-level logic optimization [15,3,4], and technology mapping [13]. However, none of these methods includes algorithms for optimal state assignment.…”

Section: Introductionmentioning

confidence: 99%

Symbolic hazard-free minimization and encoding of asynchronous finite state machines

Fuhrer¹,

Lin²,

Nowick³

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

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-This paper presents an automated method for the synthesis of multiple-input-change (MIC) asynchronous state machines. Asynchronous state machine design is subtle since, unlike synchronous synthesis, logic must be implemented without hazards, and state codes must be chosen carefully to avoid critical races. We formulate and solve an optimal hazard-free and critical race-free encoding problem for a class of MIC asynchronous state machines called burst-mode. Analogous to a paradigm successfully used for the optimal encoding of synchronous machines, the problem is formulated as an input encoding problem. Implementations are targeted to sum-of-product realizations. We believe this is the first general method for the optimal encoding of hazard-free MIC asynchronous state machines under a generalized fundamental mode of operation. Results indicate that improved solutions are produced, ranging up to 17% improvement. INTRODUCTIONThere has been a renewed interest in asynchronous design, because of their potential for high-performance, modularity and avoidance of clock skew. This paper focuses on one class of asynchronous designs: asynchronous state machines.Several methods have recently been introduced for the synthesis of asynchronous state machines [9,17,8]. These methods have been automated and produce low-latency machines which are guaranteed hazard-free at the gate-level. The design tools have benefited from a number of hazard-free optimization algorithms: exact two-level logic minimization [10], multi-level logic optimization [15,3,4], and technology mapping [13]. However, none of these methods includes algorithms for optimal state assignment. The contribution of this paper is a general method for the optimal state assignment of asynchronous state machines.Optimal state assignment of synchronous machines has been an active area of research. De Micheli [7] formulated and solved an input encoding problem, which approximates an optimal state assignment for PLA-based state machines. Other formulations as an output encoding or input/output encoding problem have also been developed [6,16,12,1].Synchronous state assignment methods are inadequate for asynchronous designs, since the resulting machines may have critical races and logic hazards. In this paper, we consider two related problems in the synthesis of asynchronousstate machines: critical race-free state encoding and hazard-free logic minimization. In existing synthesis trajectories [17,8], these problems are solved separately, where state assignment is typically performed without regard to the optimality of the eventual logic implementation,

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Logic Functions

2007

Spectral Logic and Its Applications for the Design of Digital Devices

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Asynchronous Sequential Switching Circuits

Cited by 246 publications

References 0 publications

Automatic synthesis of composable sequential quantum Boolean circuits

Automatic synthesis of composable sequential quantum Boolean circuits

Symbolic hazard-free minimization and encoding of asynchronous finite state machines

Logic Functions

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