Atmospheric Pressure Plasma Enhanced Spatial ALD of ZrO₂for Low-Temperature, Large-Area Applications

Abstract

High permittivity (high-k) materials have received considerable attention as alternatives to SiO 2 for CMOS and low-power flexible electronics applications. In this study, we have grown high-quality ZrO 2 by using atmospheric-pressure plasma-enhanced spatial ALD (PE-sALD), which, compared to temporal ALD, offers higher effective deposition rates and uses atmospheric-pressure plasma to activate surface reactions at lower temperatures. We used tetrakis(ethylmethylamino)zirconium (TEMAZ) as precursor and O 2 plasma as co-reactant at temperatures between 150 and 250 • C. Deposition rates as high as 0.17 nm/cycle were achieved with N-and C-contents as low as 0.4% and 1.5%, respectively. Growth rate, film crystallinity and impurity contents in the films were found to improve with increasing deposition temperature. The measured relative permittivity lying between 18 and 28 with leakage currents in the order of 5 × 10 −8 A/cm 2 demonstrates that atmospheric PE-sALD is a powerful technique to deposit ultrathin, high-quality dielectrics for low-temperature, large-scale microelectronic applications. The continuous improvement in performance of integrated circuits has been based on miniaturization of components. The effective gate length in field-effect transistors shrinks to smaller and smaller sizes and, consequently, the thickness of the gate oxide decreases.1 SiO 2 has been the most popular gate oxide material used in microelectronic manufacturing due to its thermal stability and ideal interface quality on Si. However, during the past fifty years the thickness of the SiO 2 gate oxide has already been reduced to its physical limit of 1.2 nm, below which a critical gate leakage of 1 A/cm 2 is exceeded. 2 To overcome this problem, dielectrics with a high permittivity (high-k materials) have been extensively investigated as promising substitutes of the conventional SiO 2 for CMOS and DRAM technology. The high permittivity (k > 10) ensures high capacitance for thicker gate oxide layers while greatly reducing tunneling and gate leakage currents. 3,4 Among high-k oxides, ZrO 2 is considered one of the most promising SiO 2 alternatives due to its high dielectric constant (k = 20-25), large bandgap (5.1-7.8 eV) and thermodynamical stability. 5,6 ZrO 2 proved to be a good dielectric in transistor applications with leakage current of the order of 10 −6 -10 −9 A/cm 2 and in DRAM capacitor applications especially when present in ZrO 2 /Al 2 O 3 /ZrO 2 nanolaminate structures.7 High-k materials are also relevant for low-power applications of flexible electronics. 5,8-11High-k materials are deposited in a variety of chemical and physical deposition techniques including metallorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), sol-gel and sputtering. ALD has proven to be the most suitable technique for high-k deposition due to its unique nanoscale thickness and layer uniformity control. In its conventional time-sequenced mode, ALD is a gas phase deposition technique in which the substrate surface is exposed altern...

High‐Throughput Atomic Layer Deposition of P‐Type SnO Thin Film Transistors Using Tin(II)bis(tert‐amyloxide)

“…[16,17] This makes sALD well-suited for highly precise, high throughput, and in-line material processing over large areas, e.g., roll-to-roll and sheet-to-sheet sALD. [18][19][20] ALD relies extensively on the underpinning reactive chemistry of precursors. As such the development of new and more reactive precursors is an essential method of improving GPC and overall deposition rate.…”

Large‐area spatial atomic layer deposition of amorphous oxide semiconductors at atmospheric pressure

“…We note that in our top‐gated SA TFTs, a low‐temperature PECVD SiO 2 gate dielectric is deposited on top of the sALD semiconductor layer, while the hydrogen doping of the semiconductor at the contact regions is mainly determined during the SiN intermetal dielectric deposition. We therefore expect that the observed bias stress behavior of sALD IGZO TFTs is not inherent to the sALD deposited material and can be further improved by modifications in the TFT stack process flow as well as by using sALD‐deposited dielectrics, in order to better control hydrogen content in the TFT stack. This is indeed demonstrated in the case of the sALD buffer layer, where it can be seen from Figure that both the positive and the negative bias stresses are improved with respect to the PECVD SiO 2 buffer layer.…”

Spatial Atomic Layer Deposition

“…Intrinsic metal oxides HfO 2 [11] Al 2 O 3 [14-16, 19-21, 26, 31, 35-50] ZnO [18,36,39,45,46,[51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67] SnO x [68,69] TiO 2 [14,18,[70][71][72] Cu 2 O [46,73,74] Nb 2 O 5 [71] NiO x [91] ZrO 2 [92,93] MoO x [94] Doped SALD has also been used for LEDs, in some cases to deposit active ZnO layers for polymer and hybrid perovskite-based diodes [54,76], and in another case using Al 2 O 3 as permeation barrier for flexible organic LEDs [49]. Other authors have also demonstrated the suitability of SALD for depositing barrier and encapsulation layers both on plastic and paper substrates [14,31,40,48].…”