Atomic hydrogen cleaning of GaAs(): a scanning tunnelling microscopy study

Khatiri, A.; Ripalda, J. M.; Krzyzewski, T. J.; Bell, GR; McConville, Christopher F; Jones, T.S.

doi:10.1016/j.susc.2003.11.007

Cited by 39 publications

(32 citation statements)

References 16 publications

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“…Atomic hydrogen (AH) cleaning has been shown in a number of studies [1][2][3][4][5][6][7][8][9][10][11][12][13][14] to be a viable alternative method for the preparation of clean, atomically flat surfaces on a variety of III-V semiconductor substrates. The technique has several advantages over conventional thermal cleaning-much lower temperatures (p400 1C) are required; impurities (in particular oxide residues) are removed more rapidly and selectively; the procedure can be performed under UHV conditions; and the presence of a group V source is not required.…”

Section: Introductionmentioning

confidence: 99%

“…Until recently, the study of AH cleaning processes on epi-ready semiconductor substrates have been mostly based on diffraction and/or spectroscopic analysis techniques [3,8,10,11], with only a relatively limited amount of evidence obtained using atomic resolution methods such as scanning tunnelling microscopy (STM) [3,7]. In this paper, we present our studies of the effects of AH exposure on the surface morphology and structure of epi-ready GaAs(0 0 1), GaAs(1 1 0) and GaAs(1 1 1)A substrates by reflection highenergy electron diffraction (RHEED) and STM.…”

Section: Introductionmentioning

confidence: 99%

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Atomic hydrogen cleaning of low-index GaAs surfaces

Khatiri

Krzyzewski

McConville

et al. 2005

Journal of Crystal Growth

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Atomic hydrogen cleaning of low-index GaAs surfaces

Khatiri

Krzyzewski

McConville

et al. 2005

Journal of Crystal Growth

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“…Previous reports showed that these experimental conditions for the atomic H cleaning on GaAs produce an atomically clean surface free of oxides. [12][13][14] The RHEED pattern was captured at 30 kV with an incident angle of 1 − 2°. The XPS data were recorded at intermediate steps in the sample preparation process using an Al K␣ 1 monochromatic source and a hemispherical analyzer.…”

mentioning

confidence: 99%

Indium stability on InGaAs during atomic H surface cleaning

Aguirre-Tostado

Milojević

Hinkle

et al. 2008

Applied Physics Letters

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Atomic H exposure of a GaAs surface at 390°C is a relatively simple method for removing the native oxides without altering the surface stoichiometry. In-situ reflection high energy electron diffraction and angle-resolved x-ray photoelectron spectroscopy have been used to show that this procedure applied to In 0.2 Ga 0.8 As effectively removes the native oxides resulting in an atomically clean surface. However, the bulk InGaAs stoichiometry is not preserved from this treatment. The In:Ga ratio from the substrate is found to decrease by 33%. The implications for high-mobility channel applications are discussed as the carrier mobility increases nearly linearly with the In content. © 2008 American Institute of Physics. ͓DOI: 10.1063/1.2919047͔One of the approaches being considered for future complementary metal-oxide-semiconductor devices is the substitution of silicon with high-mobility channels, where In x Ga 1−x As is one of the preferred candidates for metaloxide-semiconductor field-effect transistor ͑MOSFET͒ applications. 1 However, the interface thermal stability and interface quality of oxide insulators on InGaAs and other III-V semiconductors are far more complex than those on Si. Having more than one substrate element reacting with the oxide at the interface with different formation and decomposition energetics will lead to reaction channels resulting in various desorption and segregation products. 2 To preserve a stoichiometric InGaAs surface, one of the reported solutions employs an As-capping layer that is desorbed at relatively low temperatures 3,4 prior to further deposition. However, some methods for epitaxial growth of InGaAs on GaAs such as metal-organic chemical vapor deposition are not feasible with As capping. 5 An alternative to As capping includes passivation using the surface oxides which can be removed upon hydrogen plasma treatment ͑HPT͒ at a substrate temperature below 250°C, where it has been reported that no detectable surface decomposition occurs by x-ray photoelectron spectroscopy ͑XPS͒. 3,5 Atomic hydrogen treatment ͑AHT͒ from a H 2 thermal cracking source is an alternative technique for the removal of the oxide capping layer being advantageous over HPT as no H ions are supplied. This letter describes the reaction channels observed during the removal of air exposed grown native oxide on ͑13.5 nm͒ In 0.2 Ga 0.8 As/ GaAs͑001͒ upon AHT at 390°C and subsequent in-situ reflection high energy electron diffraction ͑RHEED͒ and XPS analysis. It is found that the AHT procedure results in an atomically clean ͑2 ϫ 4 reconstructed͒ In x Ga 1−x As surface. However, an indium depletion at the surface and subsurface regions is detected which may be expected to impact performance such as interface defect state densities and channel mobility in MOSFET devices. 6,7 The sample employed for this study was a commercial ͑13.5 nm͒ In 0.2 Ga 0.8 As layer grown by molecular beam epitaxy 8 on a semi-insulating GaAs͑001͒ wafer with a GaAs buffer layer of 535 nm thick. The In 0.2 Ga 0.8 As layer and GaAs buffer la...

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“…Atomic hydrogen has been demonstrated to be an effective surface preparation technique due to its ability to remove carbon-containing contaminants and native oxides (36)(37)(38). The lower temperatures required of atomic hydrogen cleaning alleviates the problems of group V desorption and surface roughening typically associated with high temperature thermal cleaning of substrates prior to epitaxial growth (36)(37)(38). A notable obstacle in III-V MOS technology is the presence of a large density of defects at the dielectric/semiconductor interface.…”

Section: Dry Etch Process Optimizationmentioning

confidence: 99%

(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options

Peralagu

Ignatova

et al. 2015

ECS Trans.

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Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

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Atomic hydrogen cleaning of GaAs(): a scanning tunnelling microscopy study

Cited by 39 publications

References 16 publications

Atomic hydrogen cleaning of low-index GaAs surfaces

Atomic hydrogen cleaning of low-index GaAs surfaces

Indium stability on InGaAs during atomic H surface cleaning

(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options

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