Atpg padding and ate vector repeat per port for reducing test data volume

Vranken, H.; Hapke, F.; Rogge, S.; Chindamo, D.; Volkerink, E.

doi:10.1109/test.2003.1271095

Cited by 28 publications

(27 citation statements)

References 26 publications

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“…Note that the TE values reported in Table XII include the control data corresponding TABLE XII RESULTS FOR IWLS-4: DYNAMIC AND STATIC SCHEDULING to TAT. Since the number of LFSR seeds is much smaller than the magnitude of the TAT, the control data contain long runs of consecutive 0 s and can be further compressed using ATE pattern repeat [30]. If we exclude the control data, the reduction in test data volume increases to 10.64× and 9.48×, respectively.…”

Section: B Experimental Resultsmentioning

confidence: 99%

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.

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Section: B Experimental Resultsmentioning

confidence: 99%

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Even though Huffman is a very effective code, further improvements can be achieved by exploiting certain ATE utilities, like the repeat command [39]. Using the repeat command, multiple successive identical logic values can be stored only once in the ATE-channel memory and they can be repeatedly transmitted over the ATE channel in successive cycles.…”

Section: Repeat-friendly Huffman Codementioning

confidence: 99%

High-Quality Statistical Test Compression With Narrow ATE Interface

Tenentes

Kavousianos

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pincount interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs.Index Terms-Defect-oriented testing, design for testability, dft, IP cores, low-power scan-based testing, multi-core SoC, selective Huffman, test data compression, unmodeled defect coverage.

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“…Vranken et al [1] discussed three alternatives to make the test data fit the ATE: (1) test memory reload -the test data are divided into several partitions -is possible but not practical due to the high time involved, (2) test data truncationthe ATE is filled as much as possible and the test data that do not fit the ATE are simply not applied -leads to reduced test quality and (3) test data compression -the test stimuli is compressed -however, does not guarantee that the test data will fit the ATE. As test memory reload is not practical, the alternatives are test data truncation and test data compression.…”

Section: Introductionmentioning

confidence: 99%

“…However, testing complex chips is becoming a problem, and one major problem is the increasing test data volume. Currently, the test data volume increases faster than the number of transistors in a design [1]. The increasing test data volume is due to (1) high number of fault sites because of the large numbers of transistors, (2) new defect types introduced by nanometer process technologies and (3) faults related to timing and delay since systems have higher performance and make use of multiple-clock domains [1].…”

Section: Introductionmentioning

confidence: 99%

Test data truncation for test quality maximisation under ATE memory depth constraint

Larsson

Edbom

2007

IET Comput. Digit. Tech.

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Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

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Atpg padding and ate vector repeat per port for reducing test data volume

Cited by 28 publications

References 26 publications

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

High-Quality Statistical Test Compression With Narrow ATE Interface

Test data truncation for test quality maximisation under ATE memory depth constraint

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