ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor

Kurth, Andreas; Riedel, Samuel; Zaruba, Florian; Hoefler, Torsten; Benini, Luca

doi:10.1109/dac18072.2020.9218661

Cited by 4 publications

(3 citation statements)

References 19 publications

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“…Several works have widely discussed the implementation of near and far AMOs [10,24,41]. Other works have tried to improve the performance of far AMOs by (i) reducing the latency between consumer and producer through data forwarding [24,68], or (ii) speeding-up lock exchange [3,20].…”

Section: A Near and Far Amo Architecturesmentioning

confidence: 99%

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DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations

Soria-Pardos

Armejach

Mück

et al. 2023

Proceedings of the 50th Annual International Symposium on Computer Architecture

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With increasing core counts in modern multi-core designs, the overhead of synchronization jeopardizes the scalability and efficiency of parallel applications. To mitigate these overheads, modern cache-coherent protocols offer support for Atomic Memory Operations (AMOs) that can be executed nearcore (near) or remotely in the on-chip memory hierarchy (far).This paper evaluates current available static AMO execution policies implemented in multi-core Systems-on-Chip (SoC) designs, which select AMOs' execution placement (near or far) based on the cache block coherence state. We propose three static policies and show that the performance of static policies is application dependent. Moreover, we show that one of our proposed static policies outperforms currently available implementations.Furthermore, we propose DynAMO, a predictor that selects the best location to execute the AMOs. DynAMO identifies the different locality patterns to make informed decisions, improving AMO latency and increasing overall throughput. DynAMO outperforms the best-performing static policy and provides geometric mean speed-ups of 1.09× across all workloads and 1.31× on AMO-intensive applications with respect to executing all AMOs near.

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Section: A Near and Far Amo Architecturesmentioning

confidence: 99%

“…Most proposals focus on using dedicated hardware (accelerators, networks, new instructions) to speed-up synchronization primitives [1,6,25,41,47,55,61,62,69]. However, these proposals incur large area overheads.…”

Section: Related Workmentioning

confidence: 99%

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations

Soria-Pardos

Armejach

Mück

et al. 2023

Proceedings of the 50th Annual International Symposium on Computer Architecture

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“…We assume the most general case where the concurrent aggregation of multiple packets in a shared aggregation buffer is executed in a critical section. Indeed, even if in principle we could use atomic operations [75], the computation would still be affected by severe contention and/or performance overhead [76,77]. Moreover, by assuming a critical section we cover the cases where the user function cannot be executed by using atomic operations, and the aggregation of sparse data that, as we will show in Section 7, requires more complex processing and in most cases needs to be executed anyhow in a mutually exclusive way.…”

Section: Aggregation Using a Single Buffermentioning

confidence: 99%

Flare: Flexible In-Network Allreduce

De Sensi,

Di Girolamo,

Ashkboos

et al. 2021

Preprint

Self Cite

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The allreduce operation is one of the most commonly used communication routines in distributed applications. To improve its bandwidth and to reduce network traffic, this operation can be accelerated by offloading it to network switches, that aggregate the data received from the hosts, and send them back the aggregated result. However, existing solutions provide limited customization opportunities and might provide suboptimal performance when dealing with custom operators and data types, with sparse data, or when reproducibility of the aggregation is a concern. To deal with these problems, in this work we design a flexible programmable switch by using as a building block PsPIN, a RISC-V architecture implementing the sPIN programming model. We then design, model, and analyze different algorithms for executing the aggregation on this architecture, showing performance improvements compared to state-of-the-art approaches. CCS CONCEPTS• Networks → In-network processing; • Hardware → Networking hardware; • Computer systems organization → Distributed architectures.

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Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads

Zaruba¹,

Schuiki²,

Hoefler

et al. 2021

IEEE Trans. Comput.

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ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor

Cited by 4 publications

References 19 publications

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations

Flare: Flexible In-Network Allreduce

Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads

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