Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads

Zaruba, Florian; Schuiki, Fabian; Hoefler, Torsten; Benini, Luca

doi:10.1109/tc.2020.3027900

Cited by 41 publications

(48 citation statements)

References 16 publications

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“…The accelerator is a 4096-core RISC-V platform that has comparable performance to current machine learning accelerators. It is organized in clusters each with 8 individual single-stage RISC-V cores [ZSHB21], each of which is accompanied by a double precision floating point unit capable of two double precision and four single precision flops per cycle. To hide memory latency, all clusters have access to a scratchpad memory and a large L2 data cache.…”

Section: Acceleratormentioning

confidence: 99%

Composite Enclaves: Towards Disaggregated Trusted Execution

Schneider

Dhar²,

Puddu

et al. 2021

TCHES

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The ever-rising computation demand is forcing the move from the CPU to heterogeneous specialized hardware, which is readily available across modern datacenters through disaggregated infrastructure. On the other hand, trusted execution environments (TEEs), one of the most promising recent developments in hardware security, can only protect code confined in the CPU, limiting TEEs’ potential and applicability to a handful of applications. We observe that the TEEs’ hardware trusted computing base (TCB) is fixed at design time, which in practice leads to using untrusted software to employ peripherals in TEEs. Based on this observation, we propose composite enclaves with a configurable hardware and software TCB, allowing enclaves access to multiple computing and IO resources. Finally, we present two case studies of composite enclaves: i) an FPGA platform based on RISC-V Keystone connected to emulated peripherals and sensors, and ii) a large-scale accelerator. These case studies showcase a flexible but small TCB (2.5 KLoC for IO peripherals and drivers), with a low-performance overhead (only around 220 additional cycles for a context switch), thus demonstrating the feasibility of our approach and showing that it can work with a wide range of specialized hardware.

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Section: Acceleratormentioning

confidence: 99%

Composite Enclaves: Towards Disaggregated Trusted Execution

Schneider

Dhar²,

Puddu

et al. 2021

TCHES

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show abstract

“…A buffer of the same size can be added for output depth slice (1), so that data transfers by the DMA engine run fully in background. 2 In total, roughly 48 KiB are required as buffers.…”

Section: Space Complexitymentioning

confidence: 99%

“…The calls to DmaWait() make sure that the data for the current iteration is present in local memory before the computation. 2 The DMA transfer buffer could be shared by the input depth slices and the filter parameters, since the total amount of data in transfer in the on-chip network does not depend on the type of data being transferred. This would save local memory in the cluster, but it requires the RTE to dynamically partition the DMA transfer buffer between different data types and variables, which is not trivial.…”

Section: Space Complexitymentioning

confidence: 99%

“…Each cluster, shown in Fig. 2, contains eight small 32-bit integer RISC-V cores [2], each paired with a large double-precision floating-point unit (FPU) [3], and 128 KiB of tightly-coupled L1 scratchpad memory (SPM) organized in 32 banks of 64 bit width each. The FPU is capable of computing one double-precision floating-point multiply-and-accumulate (MAC) operation or two single-precision MAC operations in each clock cycle.…”

Section: Introductionmentioning

confidence: 99%

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Implementing CNN Layers on the Manticore Cluster-Based Many-Core Architecture

Kurth,

Schuiki,

Benini

2021

Preprint

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“…The request for extremely efficient devices and the need for processing FP intensive workloads also led to designs that couple a tiny integer processor with bigger, performant FPUs. This is the case of Snitch [8], a tiny 32-bit integer RISC-V core extended with an FP subsystem containing: a multi-format FPU capable of single-cycle executions, optimized for performance and energy efficiency [9]; an FP register file; a set of registers to break long combinatorial paths commonly found around FPUs; a decoder; and a load-store unit. Together Snitch integer core and its FP subsystem form a Snitch core complex (CC).…”

Section: Introduction and Related Workmentioning

confidence: 99%

Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores

Bertaccini

Perotti

Mach

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In the Internet-Of-Things (IoT) domain, microcontrollers (MCUs) are used to collect and process data coming from sensors and transmit them to the cloud. Applications that require the range and precision of floating-point (FP) arithmetic can be implemented using efficient hardware floating-point units (FPUs) or by using software emulation. FPUs optimize performance and code size, whilst software emulation minimizes the hardware cost. We present a new area-optimized, IEEE 754-compliant RISC-V FPU (Tiny-FPU), and we explore the area, code size, performance, power, and energy efficiency of three different implementations of the RISC-V Instruction Set Architecture double and singleprecision FP extensions on an MCU-class processor. We show that Tiny-FPU, in its double and single-precision versions, is respectively 54% and 37% smaller than a double and singleprecision FPU optimized for performance and energy efficiency. When coupling a RISC-V core with Tiny-FPU, we achieve up to 18.5× and 15.5× speedups with respect to the same core emulating FP operations via software.

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Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads

Cited by 41 publications

References 16 publications

Composite Enclaves: Towards Disaggregated Trusted Execution

Composite Enclaves: Towards Disaggregated Trusted Execution

Implementing CNN Layers on the Manticore Cluster-Based Many-Core Architecture

Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores

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