[Authors' reply to comments on "CMOS low-noise amplifier design optimization techniques"]

CMOS single-ended-to-differential low-noise amplifier

“…For equivalent gain and IIP3 conditions in [18,19], the power consumption has been reduced by half due to the use of optimized inductors, while still keeping a good noise performance. Although [10] shows a lower NF and power consumption, it must be kept in mind that only the source degeneration inductor has been integrated; consequently the LNA performance depends mainly on the external components.…”

“…Over the years, there have appeared several design techniques for optimizing such tradeoffs. To name a few representatives, one can find the classical noise matching (CNM) technique, the simultaneous noise and input matching (SNIM) at any specified amount of power dissipation technique, the powerconstrained noise optimization (PCNO) technique, and the PCSNIM technique [10].…”

“…The inclusion of the feedback capacitor adds a new degree of freedom that allows the inclusion of the power constraint in the design. As it has been reported in [10], the LNA performance parameters are given by Schematic of a single-ended-to-differential low-noise amplifier. …”

Scaling friendly design methodology for inductively-degenerated RF low-noise amplifiers

“…The starting point of the LNA design methodologies often depends on the background of the designer. One class of methodologies starts from analytical expressions of the input impedance and the noise figure, F , given the small-signal representation of the transistor [1], [3], [4]. These analytic expressions are then used to size the circuit.…”

“…These analytic expressions are then used to size the circuit. Another class of methodologies uses the concept of noise and conjugate matching to minimize the noise figure and to maximize the power transfer of the LNA [2], [4]. These methods consider the transistors as black boxes.…”