Automated dynamic memory data type implementation exploration and optimization

Leeman, M.; Ykman, C.; Atienza, David; Florio, Vincenzo De

doi:10.1109/isvlsi.2003.1183476

Cited by 9 publications

(8 citation statements)

References 5 publications

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“…Note that we are removing one of the main issues for designers (and clear benefit on our side in the first set of experiments), because the coding and debugging of all variations of DDT implementations is already a very time-consuming process in the overall exploration time. Second, as Table 2 depicts, we have also compared our algorithm with state-of-the-art pruning and optimization methods for DDT implementations presented in [11,12,2].…”

Section: Resultsmentioning

confidence: 99%

“…Second, it includes an access component, which can refer to two different basic access patterns: sequential or iteratorbased and random access. In our case we have classified the DDT implementations in basic DDT and multi-layer implementations relevant for embedded multimedia applications, Table 1: Analytical characterization of DDT implementations considered in the exploration as proposed in [11,8]. The basic DDTs are the following ones:…”

Section: Analytical Modeling Of Ddt Implementationsmentioning

confidence: 99%

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Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation

Atienza

Baloukas²,

Papadopoulos³

et al. 2007

Proceedingsof the 10th International Workshop on Software &Amp; Compilers for Embedded Systems - SCOPES '07

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Embedded consumer devices are increasing their capabilities and can now implement new multimedia applications reserved only for powerful desktops a few years ago. These applications share complex and intensive dynamic memory use. Thus, dynamic memory optimizations are a requirement when porting these applications. Within these optimizations, the refinement of the Dynamically (de)allocated Data Type (or DDT) implementations is one of the most important and difficult parts for an efficient mapping onto low-power embedded devices.In this paper, we describe a new automatic optimization approach for the DDTs of object-oriented multimedia applications. It is based on an analytical pre-characterization of the possible elementary DDT blocks, and a multi-objective genetic algorithm to explore the design space and to select the best implementation according to different optimization criteria (i.e., memory accesses, memory footprint and energy consumption). Our results in real-life multimedia applications show that the best implementations of DDTs can be obtained in an automated way in few hours, while typically designers would require days to find a suitable implementation, achieving important savings in exploration time with respect to other state-of-the-art heuristics-based optimization methods for this task.

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Section: Resultsmentioning

confidence: 99%

Section: Analytical Modeling Of Ddt Implementationsmentioning

confidence: 99%

Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation

Atienza

Baloukas²,

Papadopoulos³

et al. 2007

Proceedingsof the 10th International Workshop on Software &Amp; Compilers for Embedded Systems - SCOPES '07

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“…Since we want to automate the process of pinpointing these DDTs (without wasting the valuable time of the designer), we choose to do an exhaustive exploration of the search space of the available DDT solutions. To assist and automate this exploration step, we developed a library-based exploration framework similar to [18,26]. We attach to each candidate DDT of the network application a profile object and run the application for one typical input trace.…”

Section: Ddt Exploration At Application-levelmentioning

confidence: 99%

“…Apart from the memory used to store the data records, the internal mechanisms of the DDTs add memory overhead to create their own internal structures and access mechanisms. Nevertheless, they can achieve great memory footprint gains in comparison to a statically allocated, compile-time memory solution [18].…”

Section: Introductionmentioning

confidence: 99%

Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement

Mamagkakis¹,

Bartzas

Pouiklis

et al. 2007

Journal of Systems Architecture

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Modern network applications require high performance and consume a lot of energy. Their inherent dynamic nature makes the dynamic memory subsystem a critical contributing factor to the overall energy consumption and to the execution time performance. This paper presents a novel, systematic methodology for generating performance-energy trade-offs by implementing optimal Dynamic Data Types, finely tuned and refined for network applications. Our systematic methodology is supported by a new, fully automated tool. We assess the effectiveness of the proposed approach in four representative, reallife case studies and provide significant energy savings and performance improvements compared to the original implementations.

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“…Conversely, MPARM simulator is particularly effective, especially in analyzing the communication infrastructure among computing nodes. Finally, several authors have explored the way to optimize the utilization of MPSoC memory hierarchy by exploring software mapping techniques [11,12,13], which are complementary approaches to the ideas proposed in this paper.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs

Sabry

Ruggiero

Valle³

2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from singlelevel on chip caches to a two-level on-chip cache hierarchy. Whereas in the embedded world there is general consensus on L1 private caches, for L2 there is still not a dominant architectural paradigm. Cache architectures that work for high performance computers turn out to be inefficient for embedded systems (mainly due to power-efficiency issues). This paper presents a virtual platform for design space exploration of L2 cache architectures in low-power Multi-Processor-Systemson-Chip (MPSoCs). The tool contains several L2 caches templates, and new architectures can be easily added using our flexible plug-in system. Given a set of constrains for a specific system (power, area, performance), our tool will perform extensive exploration to find the cache organization that best suits our needs. Through some practical experiments, we show how it is possible to select the optimal L2 cache, and how this kind of tool can help designers avoid some common misconceptions. Benchmarking results in the experiments section will show that for a case study with multiple processors running communicating tasks allocated on different cores, the private L2 cache organization still performs better than the shared one.

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Automated dynamic memory data type implementation exploration and optimization

Abstract: Abstract

Cited by 9 publications

References 5 publications

Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation

Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation

Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement

Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs

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