Automated generation of a FPGA-based oversampling model of power electronic circuits

Kiffe, Axel; Geng, Stefan; Schulte, Thomas

doi:10.1109/epepemc.2012.6397371

Cited by 13 publications

(3 citation statements)

References 12 publications

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“…Another source of error is the mis-detection of the duty cycle: the state of the switch or switches in the converter is sampled periodically. The sampling frequency can be equal to the frequency of the model update, but oversampling is usually applied [25,26]. If the sampling frequency is relatively close to the switching frequency, it might happen that the detected duty cycle is different from the real duty cycle.…”

Section: R Inmentioning

confidence: 99%

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

2021

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Hardware-in-the-loop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourth-order Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including half-bridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semi-steps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixed-point implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a low-cost field-programmable gate arrays (FPGA) (Xilinx Artix-7) achieves an integration time of 1μs. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64-bit floating point and can operate in real time with a resolution of 1μs. Therefore, the results show that this approach is suitable for modeling converters based on half-bridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (1μs) surpasses the results of techniques with even faster integration steps that do not take these events into account.

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Section: R Inmentioning

confidence: 99%

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

2021

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“…The equivalent model of the three-phase inverter using the ADC method is shown in Figure 4, and the system parameters are shown in Table 1. (15) To minimize the switching loss, the optimal Gs can be calculated via the following equation, 22 11 () 0 ( ) ( ),…”

Section: Simulation Verificationmentioning

confidence: 99%

“…Modified nodal analysis (MNA) and the state-space approach require elaborate identification of all possible circuit states of power electronics converters, which can hardly be realized in real-time simulation [12][13][14]. The Voltage-Controlled Current Source (VCCS) modeling method could obtain a precise switching state [15], but it needs the additional iterative numerical solution, which will increase the amount of calculation. The associate discrete circuit (ADC) modeling method presented by Pejovic [16,17], has a fixed admittance matrix by selecting the appropriate switch admittance parameter, Gs, which increases the simulation efficiency.…”

Section: Introductionmentioning

confidence: 99%

Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters

Guo¹,

Yuan²,

Tang³

et al. 2018

Energies

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Due to the complicated circuit topology and high switching frequency, field-programmable gate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time simulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method, which has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However, the oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this paper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance parameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource optimization method, in which the simulation time step, bit-length, and model precision are taken into consideration, is presented when the power electronics converter is implemented in FPGA. Finally, the above method is validated on the topology of a three-phase inverter with LC filters. The HIL simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the ADC modeling method, respectively.Another more general method to solve this problem is to select the optimal switch admittance parameter, Gs. One possibility is to consider a priori the switch admittance parameter, and then find the corresponding optimum value by comparing the offline simulation results with the benchmark results to minimize the relative errors; however, such a trial-and-error method has a low efficiency [19]. Within this context, the paper proposes a novel approach to choose the optimal switch admittance parameter, Gs, by minimizing the switching loss to reduce the computations required and increase the simulation precision.The high parallelism offered by FPGAs and their potential to conduct a real-time simulation in the nanosecond range make these devices an emerging processor for real-time simulation of a complex power electronic system [20][21][22][23][24]. However, due to the limited FPGA hardware resources, it is especially important to balance FPGA resource consumption and simulation accuracy. Theoretically, precise simulation results could be obtained by excessive bit-length, but it would cause unnecessary FPGA resource consumption [25,26]. Meanwhile, with the purpose of decreasing the discretization process error, the simulation time step should be set as small as possible; however, the quantization error caused by a small simulation time step may reduce the simulation accuracy [27]. Some scholars conducted a related qualitative analysis respectively but lacked overall quantitative calculations. Therefore, how to precisely select the bit-length and simulation time step is a valuable task that needs to be solved in the realm of HIL real-time simulation in FPGA. Additionally, High-Level Synthesis tools such as, Vivado High Level Synthesis (VHLS) and OpenCL SDK [28,29], allow the use of high-level languages to ease the burden of design and verification of hardware, which reduces the development time and difficulty and improves ...

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Advanced preprocessing and correction-methods for automated generation of FPGA-based simulation of power electronics

Kiffe

Riediger

Schulte

2013

2013 15th European Conference on Power Electronics and Applications (EPE)

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Automated generation of a FPGA-based oversampling model of power electronic circuits

Cited by 13 publications

References 12 publications

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

Modeling of Deadtime Events in Power Converters with Half-Bridge Modules for a Highly Accurate Hardware-in-the-Loop Fixed Point Implementation in FPGA

Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters

Advanced preprocessing and correction-methods for automated generation of FPGA-based simulation of power electronics

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