Automatic Placement Algorithms for High Packing density VLSI

Kozawa, Tokinori; Terai, Hidekazu; Ishii, Tatsuki; Hayase, M.; Miura, C.; Ogawa, Y.; Kishida, K.; Tamada, N.; Ohno, Yasuhiro

doi:10.1109/dac.1983.1585645

Cited by 19 publications

(6 citation statements)

References 3 publications

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“…Since the problem is computationally hard, several heuristics are employed to obtain a reasonable solution within constraints that include computation time and memory resources. Placement strategies for microfluidic biochips and DNA microarrays borrow ideas from rich VLSI placement literature [1], [2], [3], [4], [5], [6], [7], [8]. For biochips, the problem of problem of placement is temporal in nature.…”

Section: P Lacement Is An Important Problem In Computermentioning

confidence: 99%

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Towards Quick Solutions for Generalized Placement Problem

Srinivasan

Kamakoti

Bhattacharya

2011

2011 International Symposium on Electronic System Design

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The problem of placement is well known in Computer Aided Design (CAD) of VLSI Chips, DNA Microarrays and Microfluidic biochips. Because of the similarity of the placement problem across diverse domains a generalization of the same is reported in the literature. The generalized placement problem is an instance of the classical Quadratic Assignment Problem (QAP). In this paper, we present a new randomization based heuristic algorithm for QAP. The key to success of the proposed technique is a novel probability distribution that is employed by the heuristics to generate the necessary randomization. We show through simulation results that the proposed algorithm finds competitive solutions comparable with one of the best heuristics reported in literature, while consuming significantly smaller amount of CPU time.

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Section: P Lacement Is An Important Problem In Computermentioning

confidence: 99%

“…It is exactly these elements that satisfy the above inequality. To solve this equation for t , we compute t as if it were a real number leading to the quadratic equation (5). By solving this equation, we get some real value for t , whose integer part is used by the proposed algorithm.…”

Section: B Choosing T the Number Of Facilities To Be Replacedmentioning

confidence: 99%

Towards Quick Solutions for Generalized Placement Problem

Srinivasan

Kamakoti

Bhattacharya

2011

2011 International Symposium on Electronic System Design

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“…Their method is to order the probes in a traveling salesman problem (TSP) tour that heuristically minimizes the total Hamming distance between neighboring probes. The tour is then threaded into the 2-D array of sites using a technique similar to the one previously used in VLSI design [39]. For the same synchronous context, Kahng et al [33] suggested an epitaxial, or "seeded crystal growth," placement heuristic similar to heuristics explored in the VLSI circuit placement literature in [42] and [47].…”

Section: Physical Designmentioning

confidence: 99%

Wirelength minimization for min-cut placements via placement feedback

Kahng

Reda

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-DNA probe arrays, or DNA chips, have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis, and other genomic analyses. DNA chips are manufactured through a highly scalable process called very largescale immobilized polymer synthesis (VLSIPS) that combines photolithographic technologies adapted from the semiconductor industry with combinatorial chemistry. Commercially available DNA chips contain more than half a million probes and are expected to exceed 100 million probes in the next generation. This paper is one of the first attempts to apply very large scale integration (VLSI) computer-aided design methods to the physical design of DNA chips, where the main objective is to minimize total border cost (i.e., the number of nucleotide mismatches between adjacent sites).By exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, the authors demonstrate the potential for transfer of methodologies from the 40-year-old field of electronic design automation to the newer DNA array design field. The main contributions of this paper are the following. First, it proposes several partitioning-based algorithms for DNA probe placement that improve solution quality by over 4% compared to best previously known methods. Second, it gives a new design flow for DNA arrays, which enhances current methodologies by adding flow awareness to each optimization step and introducing feedback loops. Third, it proposes solution methods for new formulations integrating multiple design steps, including probe selection, placement, and embedding. Finally, it introduces new techniques to experimentally evaluate the scalability and suboptimality of existing and newly proposed probe placement algorithms. Interestingly, the authors find that DNA placement algorithms appear to have better suboptimality properties than those recently reported for VLSI placement algorithms (

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“…The congestion may be a global measure such as the number of nets that cross a cutline [BRE77, LAU791, or a local measure such as track density within a routing channel lPER76, KOZ83]. An even more complex congestion measure is routability mR76].…”

Section: Interconnectionmentioning

confidence: 99%

Automatic Placement A Review of Current Techniques

Preas

Karger²

1986

23rd ACM/IEEE Design Automation Conference

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This review provides an overview of the placement function within automatic layout systems. The automatic placement problem is defined and the data abstractions are described. The discussion divides placement algorithms into two classes: constructive and iterative. Applications of the algorithms within layout systems are described. A large number of references is provided to allow use as a guide to placement literature.

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Automatic Placement Algorithms for High Packing density VLSI

Cited by 19 publications

References 3 publications

Towards Quick Solutions for Generalized Placement Problem

Towards Quick Solutions for Generalized Placement Problem

Wirelength minimization for min-cut placements via placement feedback

Automatic Placement A Review of Current Techniques

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