Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata

Goli, Mehran; Stoppe, Jannis; Drechsler, Rolf

doi:10.1109/iccd.2017.65

Cited by 12 publications

(4 citation statements)

References 15 publications

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“…The existing veriication methods [9,19,19] at the ESL are not able to detect security threat models as the design functionality (and its related protocol rules) is not afected. At the ESL, there are only a few works [17,22,34] on security validation of VP-based SoCs.…”

Section: Related Workmentioning

confidence: 99%

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Goli¹,

Drechsler

2024

ACM Trans. Embed. Comput. Syst.

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Virtual Prototypes (VPs) at the Electronic System Level (ESL) are being increasingly adopted by the semiconductor industry and play an important role in modernizing the System-on-Chips (SoCs) design flow to raise design productivity and reduce time-to-market constraints. Due to their early availability and significantly faster simulation speed in comparison to Register Transfer Level (RTL) designs, VPs are used as reference models for lower levels of abstraction. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we present a novel VP-based dynamic information flow analysis approach at the ESL, consisting of three main phases which are run-time behavior extraction (in terms of transactions), transactions transformation, and security validation. The proposed approach empowers designers to validate the information flow policies of a given VP-based SoC against the most occurring security threat models which are information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including an extensive set of standard benchmarks and two real-world VP-based SoCs demonstrate the scalability and applicability of the proposed approach.

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Section: Related Workmentioning

confidence: 99%

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Goli¹,

Drechsler

2024

ACM Trans. Embed. Comput. Syst.

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“…The traffic pattern model used is the uniform, where each switch establishes communication with all the other switches, as in Figure 3. The simulations run in a SystemC TLM [19] model of the SDNoC.…”

Section: Tests Descriptionmentioning

confidence: 99%

The SDNoC Paradigm with Parallel Cores and Shortest Paths

Avelino

Oliveira

Kreutz

2022

Preprint

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Networks-on-chip provides benefits for improving distributed applications performance due to their intrinsic parallelism in communications. One promising direction for optimizing such architectures is the software defined paradigm, the software defined Networks on Chip (SDNoCs). In this approach, all routing controller mechanisms run as software in a central controller. This work proposes the optimization of SDNoCs by either exploring different routing strategies and varying the number of controllers. The approach suggests a significant improvement in communication latency by reducing the waiting time of packets in the controllers queue. The results obtained are promising. Applying Dijkstra and Branch-and-Bound algorithms and increasing the number of controller cores optimize communication latency in 100\% of the cases when compared to the XY routing strategy.

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“…The function's input arguments and local variables are also in the block (Fig. 2, lines [16][17][18][19][20][21]. Based on the extracted data, the nb_transport_bw function of the module must be traced as well as the transaction object trans (Fig.…”

Section: A Static Information Retrievalmentioning

confidence: 99%

“…For these or other situations (e.g., to validate that a given documentation still corresponds to the current state of the implementation), a way to generate a proper model from a given implementation would be desirable. Moreover, a part from the fact that knowing the properties of a given design (both structure and behavior) is necessary to understand it, this information can facilitate other steps of the design process such as debugging, validation, verification, and synthesis of the model [15], [16].…”

mentioning

confidence: 99%

Automated Nonintrusive Analysis of Electronic System Level Designs

Goli

Stoppe

Drechsler

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Due to the ever increasing complexity of hardware systems, designers strive for higher levels of abstractions in the early stages of the design process. Modeling hardware at the electronic system level (ESL) is one way to address this demand, with the C++-based system modeling framework SystemC and its abstract communication library transaction level modeling (TLM) having become de-facto standards for ESL system design. While the C++ compiler is sufficient to compile and simulate a given ESL design, for tasks of design understanding, debugging, or validation (where access to the details of design's structure and behavior is necessarily required), design needs to be processed by an appropriate tool. This problem is often solved by adding instrumentation code to either the design or the library, usually resulting in incomplete logs, work overhead and/or incompatibilities. This paper introduces an approach that automatically extracts information about both, structure and behavior of SystemC designs and TLM transactions, nonintrusively. The information is retrieved from a given design by running it in debug mode while being connected to a preprogrammed debugger, thus leaving the existing sources and workflows untouched while collecting a vast amount of data without user intervention. Illustrating use cases, value change dump files of the SystemC models' behavior and unified modeling language activity diagrams of transaction protocols are created automatically from simulation runs.

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Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata

Cited by 12 publications

References 15 publications

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

The SDNoC Paradigm with Parallel Cores and Shortest Paths

Automated Nonintrusive Analysis of Electronic System Level Designs

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