Automatic verification methodology based on structural test patterns

Abstract

Abstract

Illegal state extraction from Register Transfer Level

“…In order, to demonstrate that the extracted constraints are useful for avoiding the false error detection in our simulation-based verification approach [4], we run simulations on the VHDL models and their respective SystemC golden model, using the generated patterns. Despite the difference in the styling codes between the two models, no false errors were detected with constraints.…”

“…Recently, a simulation-based verification approach using structural (ATPG) test patterns has been proposed [4]: This approach can also be affected by ISes. Indeed, if the golden (SystemC) model and the design under verification (VHDL) model use different styling codes, forcing an invalid state will make the two models behave differently and an error will be flagged.…”