Automating DRAM Fault Mitigation By Learning From Experience

Baseman, Elisabeth; DeBardeleben, Nathan; Ferreira, Kurt Brian; Sridharan, Vilas; Siddiqua, Taniya; Tkachenko, Olena

doi:10.1109/dsn-w.2017.39

Cited by 5 publications

(1 citation statement)

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“…Their objective is to classify the faults based on prior detected errors, rather than predicting future errors. A followup work [45] extends the proposed prediction methods to predict which memory pages would experience future faults, similar to the study of Costa et al [42]. The proposed methods are trained and tested on two large HPC systems, Hopper and Cielo, and they show predictive performance improvement compared with deterministic rule-based systems.…”

Section: B Corrected Dram Errorsmentioning

confidence: 88%

Cost-Aware Prediction of Uncorrected DRAM Errors in the Field

Boixaderas

Zivanovic

Moré

et al. 2020

SC20: International Conference for High Performance Computing, Networking, Storage and Analysis

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This paper presents and evaluates a method to predict DRAM uncorrected errors, a leading cause of hardware failures in large-scale HPC clusters. The method uses a random forest classifier, which was trained and evaluated using error logs from two years of production of the MareNostrum 3 supercomputer. By enabling the system to take measures to mitigate node failures, our method reduces lost compute time by up to 57%, a net saving of 21,000 node-hours per year. We release all source code as open source.We also discuss and clarify aspects of methodology that are essential for a DRAM prediction method to be useful in practice. We explain why standard evaluation metrics, such as precision and recall, are insufficient, and base the evaluation on a cost-benefit analysis. This methodology can help ensure that any DRAM error predictor is clear from training bias and has a clear cost-benefit calculation.

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Section: B Corrected Dram Errorsmentioning

confidence: 88%