Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

Beg, Azam

doi:10.1002/cta.2031

Cited by 10 publications

(6 citation statements)

References 45 publications

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“…In [15], the authors report an automatic method for sizing the transistors in CMOS gates based on the feedback control system to optimize the gates of small and large fain-in. However, the primary goal was to enhance noise robustness.…”

Section: Related Workmentioning

confidence: 99%

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

2016

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We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.

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Section: Related Workmentioning

confidence: 99%

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

2016

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“…Joint optimization techniques usually being implemented to further improve the PPA of the design. For example, the joint technique of transistor sizing and gate length biasing [15], the joint technique of transistor sizing, body biasing, and voltage scaling [16], [17], the joint technique of transistor sizing and standard cell height tuning [7], [12], [13], and joint technique of P/N ratio selection and drive strength granularity [14]. However, among the mentioned joint optimization techniques [6], [7], [8], [9], [10], [11], [12], [13], [14], the joint optimization technique of transistor sizing and standard cell height tuning has yet to be introduced in the nearthreshold voltage operation.…”

Section: Introductionmentioning

confidence: 99%

Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage Operation

et al. 2023

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In recent decades, near-threshold voltage (NTV) design has become a well-known technique for improving the energy efficiency of digital integrated circuits. However, scaling down the operating voltage to the NTV raises two major challenges for robust operation: process variability and performance degradation. In this study, we propose a joint optimization technique for standard cell design to address the challenge of performance degradation in NTV design. The standard cell P/N ratio (PMOS width to NMOS width ratio) is being sized to maximize the performance with the constraint of a full diffusion (FD) layout structure, and the standard cell height is jointly optimized to further improve the circuit's performance or energy consumption. Increasing the standard cell height improves the circuit performance at the cost of higher energy consumption, whereas lowering the standard cell height sacrifices the circuit's performance for better energy saving. The results showed that implementing the taller library (14-track) in an AMBA high-speed bus (AHB) controller circuit can improve performance by up to 4.5%. The shortest library (7-track) resulted in 55% energy savings in the same circuit implementation. The test chip fabricated in 110-nm CMOS technology demonstrated successful operation of 8051 microcontroller down to 0.6V with the custom-designed 7-track library. The measurement results showed 4.3X energy saving compared to the operation at a supply voltage of 1.2V.INDEX TERMS CMOS digital integrated circuit, energy efficiency, near-threshold voltage, P/N ratio optimization, standard cell height.

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“…However, according to the International Technology Roadmap of Semiconductor (ITRS) , the scaling process is reaching its limits and has already started to slow down. This is owing mainly to increasing difficulties in the fabrication processes and to the impact of leakage currents . As a consequence, many new technologies are being studied as an alternative or complement to CMOS transistors.…”

Section: Introductionmentioning

confidence: 99%

Efficient and reliable fault analysis methodology for nanomagnetic circuits

Turvani

Riente

Cairo

et al. 2016

Circuit Theory & Apps

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Summary The increasing issues in scaled Complementary Metal Oxide Semiconductor (CMOS) circuit fabrication favor the flourishing of emerging technologies. Because of their limited sizes, both CMOS and emerging technologies are particularly sensitive to defects that arise during the fabrication process. Their impact is not easy to analyze in order to take the necessary countermeasures, especially in the case of circuits of realistic complexity based on emerging technologies. In this work, we propose a new methodology supported by an efficient and reliable tool for the identification of the impact of faults in complex circuits implemented using the emerging technology we are focusing on in this case: nanomagnetic logic. The methodology is based on three main steps: (i) we performed exhaustive physical‐level simulations of basic blocks based on a detailed finite‐element tool in order to have a full characterization, to know their properties in presence of defects, and to have a solid reference point for the following steps; (ii) we developed a model (fanomag) for the basic block behavior suitable for simulations in presence of defects of complex circuits, that is, lighter than a physical level one, but accurate enough to capture the most important features to be inherited at circuit level; (iii) starting from a physical design of complex circuits that we perform using a specific design tool we developed, that is, ToPoliNano, we simulated using fanomag, now embedded in our ToPoliNano tool, the behavior of circuits in presence of multiple sets of fabrication defects using a Monte Carlo approach now included in ToPoliNano as a new feature. In this paper, a specific type of defect is considered as a case study. The framework and methodology are conceived to be easily extended to handle other types of defects and problems due to working conditions that a designer and/or a technologist might want to focus on. The major outcome is then a powerful methodology and tool capable to analyze with a good accuracy nanomagnetic logic complex circuits and architectures both in ideal conditions and in presence of defects with remarkable performance in terms of simulation times. Copyright © 2016 John Wiley & Sons, Ltd.

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Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

Cited by 10 publications

References 45 publications

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage Operation

Efficient and reliable fault analysis methodology for nanomagnetic circuits

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