Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery

Stojanović, Vladimir; Ho, A.; Garlepp, B.W.; Chen, F.; Wei, J.; Tsang, G.; Alon, Elad; Kollipara, Ravi; Werner, C.; Zerbe, J.; Horowitz, Mark

doi:10.1109/jssc.2004.842863

Cited by 133 publications

(77 citation statements)

References 11 publications

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“…At the receiver, these particular sequences could be detected and a timing interval could be calculated from the mean transition timing. The coefficients would be transmitted back to the transmitter in a back-channel scheme [3].…”

Section: Phase Pre-emphasismentioning

confidence: 99%

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Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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Abstract-A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase preemphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s.

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Section: Phase Pre-emphasismentioning

confidence: 99%

“…Pre-emphasis-based equalization in the transmitter and decision feedback equalization in the receiver figure prominently in overcoming signal degradation and improving the bit-error rate (BER) [1]- [3]. Currently, one challenge of equalization is minimizing power consumption while still improving signal integrity in the presence of attenuation and reflections.…”

mentioning

confidence: 99%

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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show abstract

“…[nm] need for a Digital-to-Analog Converter (DAC) at the transmitters, an Analog-to-Digital Converter (ADC) at the receiver, and complex clock recovery schemes [17][18][19][20][21][22][23][24]. High-order PAM was also used for wireline communications to improve spectral efficiency.…”

Section: Referencesmentioning

confidence: 99%

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Yuan¹

2014

J Elec Electron Syst

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“…This equalized link architecture is very similar to the stateof-the-art off-chip high-speed links [10], where the first DFE tap is usually predictive due to speed constraints. The important difference in on-chip links is that good ISI compensation can be achieved with relatively short equalizer filters and transmitter impedance is not necessarily fixed to 50 Ω.…”

Section: Equalized Link Design Spacementioning

confidence: 99%

“…By using the epigraph form and expanding the l 1 -norm terms in (10) and (11) (12) can be rather slow, so we use the numerical gradient solver on original problem in (11) to directly compute the l 1 -norms. Although it speeds up the computation, this method is still about an order of magnitude slower than the closed-form least-mean-square equalization (LMSE) algorithm described next.…”

Section: A) Maximizing the Worst-case Eye Opneing (1 1 -Norm Solution)mentioning

confidence: 99%

Equalized interconnects for on-chip networks: modeling and optimization framework

Kim¹,

Stojanović²

2007

2007 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-This paper presents a modeling framework for fast design space exploration and optimization of equalized on-chip interconnects. The exploration is enabled by cross-layer modeling that connects the transistor and wire parameters to link performance, equalization coefficients, and architecturefriendly metrics (delay, energy-per-bit, and throughput density). Appropriate models are derived to speed-up the search by more than two orders of magnitude and make a million point design space searchable in less than two hours on a standard machine. With this approach we are able to find the best link design for target throughput, power and area constraints, thus enabling the architectural optimization of energy-efficient on-chip networks. For the same latency and throughput density, equalized interconnects optimized using the new methodology have up to 10x better energy-efficiency than optimized repeater interconnects.

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Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery

Cited by 133 publications

References 11 publications

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Equalized interconnects for on-chip networks: modeling and optimization framework

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