Equalized interconnects for on-chip networks: modeling and optimization framework

Abstract

Abstract-This paper presents a modeling framework for fast design space exploration and optimization of equalized on-chip interconnects. The exploration is enabled by cross-layer modeling that connects the transistor and wire parameters to link performance, equalization coefficients, and architecturefriendly metrics (delay, energy-per-bit, and throughput density). Appropriate models are derived to speed-up the search by more than two orders of magnitude and make a million point design space searchable in less than two hours on a standard machine. With this approach we are able to find the best link design for target throughput, power and area constraints, thus enabling the architectural optimization of energy-efficient on-chip networks. For the same latency and throughput density, equalized interconnects optimized using the new methodology have up to 10x better energy-efficiency than optimized repeater interconnects.

Machine Learning Based Energy-Efficient Design Approach for Interconnects in Circuits and Systems

“…A typical data transmission that system includes driver, receiver, and interconnect is shown in Figure 1 below. While most effort has been concentrated on the on-chip circuit and interconnects' optimization [2][3][4][5][6][7][8], the energy-aware off-chip interconnect optimization in the transceiver circuit has not been investigated thoroughly so far [9,10]. The authors in [2][3][4] focused on energy-efficient on-chip interconnect design.…”

Modeling of CMS‐based nonuniform interconnects using FDTD technique

“…4 The noise in 2,3 Due to the intersymbol interference problem in the received signal, the bit error rate increases eventually.…”

“…Different procedures, to be specific decision feedback equalization, linear equalization, pre-emphasis, deemphasis, and adaptive equalization, have been accounted for equalization techniques in interconnects. 4 The noise in interconnects emerges mostly due to resistive heating and coupling between the lines that packed closely. 5 The coupled on-chip interconnects face thermal noise due to resistive heating, 6 which limits the current density and causes the breakdown.…”

“…4 The noise in For accurate analysis, the nonlinear CMOS inverter is used as a driver for coupled nonuniform interconnects.…”

“…Different procedures, to be specific decision feedback equalization, linear equalization, pre-emphasis, deemphasis, and adaptive equalization, have been accounted for equalization techniques in interconnects. 4 The noise in…”