Band offset induced threshold variation in strained-Si nMOSFETs

Goo, Jung-Suk; Qi, Xiang; Takamura, Yayoi; Arasnia, F.; Paton, E.; Besser, Paul R.; Pan, James N.; Lin, Ming-Ren

doi:10.1109/led.2003.815431

Cited by 50 publications

(10 citation statements)

References 15 publications

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“…The V th shift corresponds to a Ge concentration of 3 -5% in a strained-Si/ SiGe substrate. [21][22][23][24][25] The shape of this R on -V th plot is not markedly changed, thus, almost the same V th and R on shifts occur at each LDMOS transistor. As a matter of fact, 3 of V th in a wafer is slightly increased from 30.8 to 31.2 mV, Pepi / P ++ Substrate Deep Trench Etch Etch Back B-doped Amorphous-Si Depo.…”

Section: Resultsmentioning

confidence: 89%

Strain-Controlled Laterally Diffused Metal–Oxide–Semiconductor Transistor Utilizing Buried-Polysilicon Sinker as Stressor

Miyamoto¹,

Sugii

Kumagai

et al. 2010

Jpn. J. Appl. Phys.

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In this paper we analyse in detail the KKR CPA calculations of Pindor er al on the electronic structure of a series of non-stoichiometric Pd-rich Pd-Ag hydrides. We find the hydrogen-metal bonding band split off the bottom of the metal d bands for all H concentrations. We study the electronic structure at high symmetry points and along the T L direction, and in particular we find two L1, states. We comment on the relationship of our results to the stability of hydride formation.Ber. Bunsenges Phys. Chem. 16 535

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Section: Resultsmentioning

confidence: 89%

Strain-Controlled Laterally Diffused Metal–Oxide–Semiconductor Transistor Utilizing Buried-Polysilicon Sinker as Stressor

Miyamoto¹,

Sugii

Kumagai

et al. 2010

Jpn. J. Appl. Phys.

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“…The threshold voltage shift could be due to the splitting of valence band edges by the compressive strain. 9,10) As channel length decreases, the threshold voltage difference between the control and strain samples becomes more dramatic, as shown in Fig. 5.…”

Section: Device Characteristicsmentioning

confidence: 89%

Device Characteristics and Aggravated Negative Bias Temperature Instability in p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Uniaxial Compressive Strain

Lin

Chang

et al. 2006

jjap

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P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) featuring poly-SiGe gates and compressive strain channels were investigated. The compressive strain in the channel was deliberately induced in this study by a plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) capping layer over the gate. Our results indicate for the first time that, while strain channel engineering serves as an effective method to enhance drive current for scaled complementary metal–oxide–semiconductor (CMOS) devices consistent with literature reports, it also simultaneously aggravates the negative bias temperature instability (NBTI) of scaled devices. The aggravated NBTI behavior is ascribed to a higher amount of hydrogen incorporation during SiN deposition as well as a higher strain energy stored in the channel. Saturation phenomena in the shift of threshold voltage and generation of interface states are observed at high stress temperatures and long stress times. Moreover, transconductance degradation in devices with SiN capping is greatly aggravated under high temperature stress.

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“…The threshold voltage is the minimum value of gate to source voltage (V GS ) at which a channel is established by the gate oxide at the surface of the 4H-SiC MOSFET. Therefore, in a 4H-SiC MOSFET, the threshold voltage is taken to be that value of V GS for which the surface potential is equal to twice the difference between the intrinsic and extrinsic Fermi level f F Si , [9,10,[12][13][14][15]:…”

Section: Threshold Voltage Modelmentioning

confidence: 99%

A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale

Yadav

Pradhan

Sahu

2016

Adv. Nat. Sci: Nanosci. Nanotechnol.

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Analytical modeling with a verified simulation setup of surface potential, threshold voltage and electric field for a 4H-SiC MOSFET is presented to make enquiries about the short channel effects. The two-dimensional (2D) Poisson equation is used to achieve the model for surface potential. The 2D position equations have been solved by using four boundary conditions. The detail of the model is appraised by the various MOSFET parameters such as silicon carbide thickness, body doping concentration, and gate oxide influencing the electric field, channel potential and threshold voltage. The outcome shows that this model can reduce the short channel effects, drain induced barrier lowering and advance the sub-threshold fulfillment in nanoelectronic applications as compared to silicon MOSFETs. By comparing the model results with the 2D device simulations the veracity of the suggested 2D analytical model is proven.

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Band offset induced threshold variation in strained-Si nMOSFETs

Cited by 50 publications

References 15 publications

Strain-Controlled Laterally Diffused Metal–Oxide–Semiconductor Transistor Utilizing Buried-Polysilicon Sinker as Stressor

Strain-Controlled Laterally Diffused Metal–Oxide–Semiconductor Transistor Utilizing Buried-Polysilicon Sinker as Stressor

Device Characteristics and Aggravated Negative Bias Temperature Instability in p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Uniaxial Compressive Strain

A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale

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