Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism

Abstract

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On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

“…Since their testing was done off-line with an external ATE, they focused on maximizing the utilization of available NoC bandwidth for transporting test data by reducing the "idle bits" [13] or by using a Time-Division-Multiplexed NoC [14].…”