2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools 2010
DOI: 10.1109/dsd.2010.16
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On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

Abstract: Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propo… Show more

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Cited by 9 publications
(8 citation statements)
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References 13 publications
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“…Figure 3 shows the Dependability Manager (DM), positioned in the bottom left corner of each RFD. This tile provides hardware support to perform structural tests of the XENTIUM R cores, using the NoC as test access mechanism [21]. Using the principle of majority voting, triples of XENTIUM R cores are tested for faults.…”
Section: B Platform Discovery and Fault Detectionmentioning
confidence: 99%
“…Figure 3 shows the Dependability Manager (DM), positioned in the bottom left corner of each RFD. This tile provides hardware support to perform structural tests of the XENTIUM R cores, using the NoC as test access mechanism [21]. Using the principle of majority voting, triples of XENTIUM R cores are tested for faults.…”
Section: B Platform Discovery and Fault Detectionmentioning
confidence: 99%
“…Previous studies have suggested that the NoC can be reused as a Test Access Mechanism (TAM) to avoid dedicated test buses [20]. Recent research has shown simulation results of performing a scanbased structural test using the NoC as a TAM at application run-time in an MPSoC [21].…”
Section: Mpsoc Architecture and System Maintainabilitymentioning
confidence: 99%
“…Each Xentium tile processor has 32 parallel scan-chains for conventional manufacturing tests and dependability structural tests. An IEEE 1500 compliant dependability wrapper has been developed to switch the Xentium tiles to normal, manufacturing test and dependability test modes [21]. Other important dependability infrastructures include BIST for the SRAM block and a software-based self-test for the interconnection nodes such as the NoC and MCPs.…”
Section: B Design For a Dependable Rfdmentioning
confidence: 99%
“…The multiple wrapped, processing tiles in the MPSoC are interconnected by a packaged-switched NoC. This NoC is also reused as a Test Access Mechanism (TAM) [16] to transport test stimuli and test responses when the processing tiles are being tested at application run-time. Since the total bandwidth of the NoC is shared between the application data and the dependability test data, dynamically pausing and resuming of the scan-based test is used to ensure sufficient NoC bandwidth is available for the running applications.…”
Section: B Dependability Of Ipsmentioning
confidence: 99%