Bandwidth-aware reconfigurable cache design with hybrid memory technologies

Zhao, Xiujian; Xu, Jun; Xie, Weibo

doi:10.1109/iccad.2011.6105304

Cited by 18 publications

(15 citation statements)

References 22 publications

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“…Zhao et al [14] propose a hybrid cache hierarchy where each level is designed with a memory technology such that the bandwidth provided by the overall hierarchy is optimized. They study the write endurance, latency, energy and bandwidth of different technologies.…”

Section: Sram+sttram Hybrid Cachesmentioning

confidence: 99%

“…Also, in hybrid caches, early eviction of dead blocks from SRAM improves its utilization [55]. The dynamic cache reconfiguration based techniques [12,14] work on the principle that there exists large variation in intraapplication and inter-application cache requirement of different programs. Thus, by only allocating suitable amount of cache to an application in each phase, significant amount of energy can be saved.…”

Section: Classification and Overviewmentioning

confidence: 99%

“…Characteristics of Different Memory Technologies[6][7][8][9][10][11][12][13][14][15][16][17][18] (R/W = read/write)…”

mentioning

confidence: 99%

See 2 more Smart Citations

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches

Mittal

Vetter

Liu

2015

IEEE Trans. Parallel Distrib. Syst.

126

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Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of onchip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight their similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems. Index Terms-Review, classification, embedded DRAM (eDRAM), non-volatile memory (NVM), spin-transfer torque RAM (STT-RAM), resistive RAM (RRAM), phase change RAM (PCM), domain wall memory (DWM), emerging memory technologies.

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Section: Sram+sttram Hybrid Cachesmentioning

confidence: 99%

Section: Classification and Overviewmentioning

confidence: 99%

See 1 more Smart Citation

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches

Mittal

Vetter

Liu

2015

IEEE Trans. Parallel Distrib. Syst.

126

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show abstract

“…Consequently, memory bandwidth becomes one of the most important factors that influence high performance system design. To address the bandwidth issue, Zhao et al [61] proposed a bandwidth-aware reconfigurable cache hierarchy to enhance system performance of multicore processors with hybrid memory technologies, by leveraging NVM's bandwidth benefits at large capacities. The hybrid cache hierarchy maximizes the provided bandwidth of processor caches and minimizes the bandwidth demand to the off-chip main memory.…”

Section: Processor Cache Design With Nvmsmentioning

confidence: 99%

Memory and Storage System Design with Nonvolatile Memory Technologies

Zhao

Chi

et al. 2015

IPSJ Transactions on System LSI Design Methodology

Self Cite

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Abstract:The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance and energy efficiency provided by traditional memory technologies. As a result, computer architects are facing significant challenges in developing high-performance, energy-efficient, and reliable memory hierarchies. New byte-addressable nonvolatile memories (NVMs) are emerging with unique properties that are likely to open doors to novel memory hierarchy designs to tackle the challenges. However, substantial advancements in redesigning the existing memory and storage organizations are needed to realize their full potential. This article reviews recent innovations in rearchitecting the memory and storage system with NVMs, producing high-performance, energy-efficient, and scalable computer designs.

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“…In recent years, several proposals, either at the circuit or architecture level [Wu et al 2009;Zhao et al 2010;Zhou et al 2009;Rasquinha et al 2010], have been made to address the energy and latency challenges of STT-RAM writes. Another approach for mitigating write problem of STT-RAM cells is device-level optimizations.…”

Section: Introductionmentioning

confidence: 99%

Architecting the Last-Level Cache for GPUs using STT-RAM Technology

Samavatian

Arjomand

Bashizade

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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Future GPUs should have larger L2 caches based on the current trends in VLSI technology and GPU architectures toward increase of processing core count. Larger L2 caches inevitably have proportionally larger power consumption. In this article, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology. Due to its high-density and low-power characteristics, STT-RAM technology can be utilized in GPUs where numerous cores leave a limited area for on-chip memory banks. They have, however, two important issues, high energy and latency of write operations, that have to be addressed. Low retention time STT-RAMs can reduce the energy and delay of write operations. Nevertheless, employing STT-RAMs with low retention time in GPUs requires a thorough study on the behavior of GPGPU applications. Based on this investigation, we have architectured a two-part STT-RAM-based L2 cache with low-retention (LR) and high-retention (HR) parts. The proposed two-part L2 cache exploits a dynamic threshold regulator (DTR) to efficiently regulate the write threshold for migration of the data blocks from HR to LR, based on the behavior of the applications. Also, a Data and Access type Aware Cache Search mechanism (DAACS) is hired for handling the search of the requested data blocks in two parts of the cache. The STT-RAM L2 cache architecture proposed in this article can improve IPC by up to 171% (20% on average), and reduce the average consumed power by 28.9% compared to a conventional L2 cache architecture with equal on-chip area.

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Bandwidth-aware reconfigurable cache design with hybrid memory technologies

Cited by 18 publications

References 22 publications

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches

Memory and Storage System Design with Nonvolatile Memory Technologies

Architecting the Last-Level Cache for GPUs using STT-RAM Technology

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