ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)
DOI: 10.1109/iscas.1999.777881
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Behavioral modeling of charge pump phase locked loops

Abstract: The CP-PLL5 is a typical mixed signal device; there is no general theory to describe exactly the dynamics of its non-linear transient. Many models have been presented to model the behavior of the PLLs. A discrete linear model, a discrete non-linear model and an event-driven model of the second order PLL have been proposed. A comparison of these models with a transistor level model will show that the event-driven model is the most accurate. Moreover the computational effort of these models for a given accuracy … Show more

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Cited by 21 publications
(9 citation statements)
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“…off-locking) and the phase error is |φ err | ≥2π [6]- [10]. It has a very monotonic transient when it is approached on-locking, where both incoming signals are well synchronized in frequency and triggering edges are falling successive to each other (↓ ref , ↓ div ⇔ |φ err |<2π) [7]- [10], [14]. It is a very challenging task for designer/analyst to predict the behavior of CP-PLL without using any exact system level description.…”
Section: Introductionmentioning
confidence: 99%
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“…off-locking) and the phase error is |φ err | ≥2π [6]- [10]. It has a very monotonic transient when it is approached on-locking, where both incoming signals are well synchronized in frequency and triggering edges are falling successive to each other (↓ ref , ↓ div ⇔ |φ err |<2π) [7]- [10], [14]. It is a very challenging task for designer/analyst to predict the behavior of CP-PLL without using any exact system level description.…”
Section: Introductionmentioning
confidence: 99%
“…The sampled nature of the CP-PLL is another constraint to linear analysis. However discrete-time (DT) non-linear methods are more efficient and growing methodology for characterizing the timing based switching state of the CP-PLL [6]- [14]. The DT event-driven (ED) approach provides an ultra-fast (few seconds simulation time) simulation, exact system level and iterative representation of the system by allowing its modular concept [6]- [12].…”
Section: Introductionmentioning
confidence: 99%
“…Different behavioral models for PLL systems are presented for purely PLL simulation and verification [4][5][6][7]22]. A recent approach for hierarchical PLL design [17] focuses mainly on the jitter-power trade-off in the VCO design.…”
Section: Circuit Sizingmentioning
confidence: 99%
“…But the s-domain analysis is based on a continuous time approximation of the CPPLL and can not accurately estimate the locking time. Besides s-domain analysis, two analyses using an event-driven non-linear model for a 2nd-order CPPLL in [5] and state-space equations for a 3rd-order CPPLL in [12] are proposed, which can provide exact models of the PLL dynamics. But it is difficult to set up or adapt these equations to other architectures especially for higher-order PLLs.…”
Section: Charge Pump Pllmentioning
confidence: 99%
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