2019 IEEE International Symposium on Circuits and Systems (ISCAS) 2019
DOI: 10.1109/iscas.2019.8702123
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BEOL NEM Relay Based Sequential Logic Circuits

Abstract: In recent years Nano-electromechanical (NEM) relays have been proposed as promising candidates to complement or replace CMOS technology in ultra-low power applications, due to their zero off-state leakage and abrupt turn on/off behavior. The development of the air gap technology enables the implementation of vertical relays, compatible with the Back-End-of-Line (BEOL) CMOS fabrication processes. In this work, we present the design, implementation, and analysis of integrated sequential logic blocks built with B… Show more

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Cited by 5 publications
(5 citation statements)
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“…7(c IV. DISCUSSION With relay logic implemented [19], relay circuits only endure one tM between output and inputs. Though relays are inevitably slower than transistors, this difference becomes smaller when the circuit complexity increases, as CMOS circuits suffer from quadratically increased Elmore delay.…”
Section: Design and Demonstration Of Relay Circuitsmentioning
confidence: 99%
See 1 more Smart Citation
“…7(c IV. DISCUSSION With relay logic implemented [19], relay circuits only endure one tM between output and inputs. Though relays are inevitably slower than transistors, this difference becomes smaller when the circuit complexity increases, as CMOS circuits suffer from quadratically increased Elmore delay.…”
Section: Design and Demonstration Of Relay Circuitsmentioning
confidence: 99%
“…It also partially compensates for the larger device footprint. Relay-based JK flip-flop [19] uses 20, while the CMOS counterpart uses 36 devices. Relay 4-bit DAC (digital-toanalog converter) and ADC (analog-to-digital converter) can be built with 84 and 116 devices [24], while the CMOS way would need 160 and 343, respectively.…”
Section: Design and Demonstration Of Relay Circuitsmentioning
confidence: 99%
“…When CLK is low, the output holds its value, and when CLK becomes high, the circuit is in evaluation mode and the input D is presented at the output. By using the relay logic introduced in [24] and arranging the gate driving signals such that they arrive at gate terminals simultaneously, the output of the relay circuits proposed in this work will be valid after only one mechanical delay when inputs are valid.…”
Section: A Relay Circuits Designmentioning
confidence: 99%
“…For instance, MEM relays have been used as transmit/receive switches and antenna tuners in radios [ 2 ]. Recent work has also explored the application of MEM relays to digital circuit design, examining their potential as logic gates [ 3 ], power gates [ 4 ], and back-end-of-line integrated switches [ 5 , 6 ].…”
Section: Introductionmentioning
confidence: 99%