Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

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With the fundamental limitation on transistor scaling and energy efficiency, Nano-electromechanical (NEM) relays have emerged as a promising alternative solution for ultralow power integrated circuits due to their zero leakage and steep subthreshold properties. In this paper, we explore the implementation of the I/O interface circuits, namely the analog-todigital converter (ADC) and the digital-to-analog converter (DAC), with back-end-of-line (BEOL) NEM relays. The proposed design for the ADC comparators eliminates the need for reference generation by utilizing a bank of NEM relays with different pullin voltages. The decoder and encoder of both data converters are optimized by using a minimum number of devices and exclusive, non-leaking paths for each input and output code. As a result, while the sampling rate and operation frequency of the relaybased converters are inherently lower than CMOS counterparts due to mechanical nature of operation, the proposed data converters can achieve at least one order of magnitude lower energy consumption, which makes them appealing alternatives for ultra-low power VLSI and Internet of Things (IoT) applications.

In recent years Nano-electromechanical (NEM) relays have been proposed as promising candidates to complement or replace CMOS technology in ultra-low power applications, due to their zero off-state leakage and abrupt turn on/off behavior. The development of the air gap technology enables the implementation of vertical relays, compatible with the Back-End-of-Line (BEOL) CMOS fabrication processes. In this work, we present the design, implementation, and analysis of integrated sequential logic blocks built with BEOL NEM relays, using custom and commercial modeling and simulation tools. While relay circuits are inevitably slower than transistor counterparts due to the mechanical nature of the operation, we show that the proposed circuits offer more than one order of magnitude saving on energy and area consumption. This is particularly attractive in the Internet of Things (IoT) applications, where the requirements for ultra-low power consumption are significantly stricter than those for computation speed.

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