Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations

Linn, Eike; Rosezin, R.; Tappertzhofen, Stefan; Böttger, U.; Waser, Rainer

doi:10.1088/0957-4484/23/30/305205

Cited by 340 publications

(268 citation statements)

References 34 publications

Supporting

Mentioning

267

Contrasting

Order By: Relevance

“…So far a variety of approaches has been proposed for synthesis of logic-in-memory computing circuits, mostly based on material implication (IMP: p → q =p ∨ q) [12], [13] and some using other basic operations [14], [15], [11]. In all these approaches, the target function can only be executed using a certain number of RRAM devices and after a number of operations, which increases rapidly as the size of the function increases.…”

Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

Endurance management for resistive Logic-In-Memory computing architectures

Shirinzadeh

Soeken

Gaillardon

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

View full text Add to dashboard Cite

Abstract-Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.

show abstract

Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

Endurance management for resistive Logic-In-Memory computing architectures

Shirinzadeh

Soeken

Gaillardon

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

View full text Add to dashboard Cite

show abstract

“…Resistive memories have the capability of natively implementing a universal majority-based logic operator [10]. Indeed, by denoting Z the value stored in the memory, after the application of signals on its top and bottom terminals, denoted P and Q, it is possible to express the updated value of Z as Z ← P Z ∨ QZ ∨ P Q = P QZ .…”

Section: Plim Architecturementioning

confidence: 99%

“…The instruction set for the PLiM consists of a single instruction called RM3, which computes the majority-of-three operation in which one input is inverted. This corresponds directly to the physical implementation of the RRAM proposed in [10]. Consequently, Majority-Inverter Graphs (MIG, [3]), which are logic representations that use the majorityof-three operation and inverters as only logic primitives, are the natural abstraction to derive PLiM programs, i.e., sePermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Section: Introductionmentioning

confidence: 95%

An MIG-based compiler for programmable logic-in-memory architectures

Soeken

Shirinzadeh

Gaillardon

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

View full text Add to dashboard Cite

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on resistive memory arrays. Our approach uses Majority-Inverter Graphs (MIGs) to manage the computational operations. In order to obtain a performance and resource efficient program, we employ optimization techniques both to the underlying MIG as well as to the compilation procedure itself. In addition, our proposed approach optimizes the program with respect to memory endurance constraints which is of particular importance for in-memory computing architectures.

show abstract

“…ReRAM has several attractive properties, such as fast operation, low power consumption, multilevel single-cell storage, and very high integration density (4F 2 footprint, where F is the minimum feature size of the process technology), owing to the simple, dense, high-connectivity structure of the nanocrossbar geometry [6], [7]. Additionally, a paradigm shift is needed in computing systems beyond the classical and so far dominant von Neumann architecture, which separates storage from computation in distinct units [8]. Data processing in von Neumann systems is normally carried out sequentially, thus requiring a lot of information exchange and communication between the central processing unit(s) (CPU(s)) and data storage module(s).…”

Section: Introductionmentioning

confidence: 99%

Crossbar-Based Memristive Logic-in-Memory Architecture

Papandroulidakis

Vourkas

Abusleme

et al. 2017

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

Aquesta és una còpia de la versió draft d'un article publicat a IEEE transactions on nanotechnologyhttp://hdl.handle.net/2117/104473 Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501. DOI: 10.1109/TNANO.2017 © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1Abstract-The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We present an analysis of circuit resources, integration density, and logic computation parallelism and prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder (HA) and sum-of-products logic functions.

show abstract

Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations

Cited by 340 publications

References 34 publications

Endurance management for resistive Logic-In-Memory computing architectures

Endurance management for resistive Logic-In-Memory computing architectures

An MIG-based compiler for programmable logic-in-memory architectures

Crossbar-Based Memristive Logic-in-Memory Architecture

Contact Info

Product

Resources

About