Bilateral Testing of Nano-scale Fault-Tolerant Circuits

Security and fault tolerance evaluation of TMR–QDI circuits

“…As long as no more than one of the modules fails, the output of the voter is the same as the outputs of the two other fault-free modules. The degree of fault tolerance is defined as the maximum number of faults that can be tolerated in a system [42]. Fig.…”

“…In order to show the tolerance of the resistive bridging faults, we have used and adapted the case given by Fang and Hsiao [42] (when double stuck-at defects affect two different modules). In this work, we consider that two resistive bridge faults F 1 and F 2 affect two different modules of the TMR.…”

“…The fault tolerance of transient faults is discussed also by Zhang et al [46] and Kuang et al [47]. However, these works do not address the security and fault tolerance evaluation of TMR secure systems against resistive bridges defect, which are still the dominant defect for manufacturing process [48] and are more difficult to detect in a TMR structure due to the presence of redundancy [42]. The aim of our simulations is to evaluate the fault-tolerance and the security of A lot of work has focused on fault models of resistive bridge defects [35,36] and throughout our simulations, we used the one proposed in [36], which describes the resistive bridge fault impact considering the static and dynamic behaviour of the circuit.…”

Yield Improvement, Fault-Tolerance to the Rescue?

“…To increase the yield for future VLSI systems, fault tolerant architectures have been proposed as a potential solution [1]. Fault tolerant architectures are commonly used to tolerate on-line faults, i.e.…”