Bipolar Transistor Excess Phase Modeling in Verilog-A

McAndrew, Colin C.; Huszka, Z.; Coram, G.J.

doi:10.1109/jssc.2009.2022667

Cited by 5 publications

(6 citation statements)

References 8 publications

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“…The second‐order Bessel filter adjunct network used in the VBIC and HICUM models is shown on Figure . In the VBIC model, the delay time TD is constant and the Verilog‐A implementation is performed with k = 1.…”

Section: Case Studiesmentioning

confidence: 99%

“…In the HICUM models, the transit time tf and consequently the delay time is bias dependent. Adopting a scaling factor of k = t 0/ tf as proposed in McAndrew et al, the undesired effect of the derivatives can be eliminated. Here, t0 is a model parameter representing transit time at low currents and zero collector‐base voltage Vcb.…”

Section: Case Studiesmentioning

confidence: 99%

“…Phase of y21 in HICUML0V1p32 at Vcb = 0 and f = 2 GHz. Solid line: release (scaled), circles: discretization by the floor() function, stars: discretization by integer conversion, dashed: no NQS…”

Section: Case Studiesmentioning

confidence: 99%

“…The problem could be solved by adopting a scaling with t 0 / TD to the adjunct network. It puts a constant t 0 time parameter in the charge terms while relocated TD to the non–energy‐storing components . This avoided the generation of the TD derivatives in the charge elements.…”

Section: Introductionmentioning

confidence: 99%

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Suppressing derivatives of selected variables in Verilog‐A

Huszka

Molnar

2019

Circuit Theory & Apps

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A former scaling technique made it possible to eliminate the effect of the automatically generated derivatives at bipolar non-quasi-static (NQS) modeling in Verilog-A. An alternative technique is proposed here, which makes the derivatives of selected variables zero. The method was verified on the examples of bipolar NQS variants. The confirming results open a new perspective for increasing the flexibility of Verilog-A compact modeling along with the reduction of computational efforts. KEYWORDS bipolar transistor, compact model, derivative management, non-quasi-static effects, Verilog-A | INTRODUCTIONThe Verilog-A analog subset 1 of hardware description languages has become the standard for defining compact models. 2 It has been accepted and recommended for this purpose by the Compact Modeling Coalition. 3 It enables model construction focusing primarily on device physics with none or just a minimal consideration for numerical algorithms. These details are left primarily on a new program block the Verilog-A compiler. 4-6 It translates the model instructions to C++ code, which can be used either directly or typically after some further optimizations by the simulator providers.One of the main features of this compiler is the automated computation of the derivatives with respect to the system variables. The derivatives are needed for the robust solution of the system matrix by the Newton-Raphson (NR) method. The matrix linearized this way provides the basis for small signal analysis.The hand-coded derivatives often led to slow or no convergence; therefore, their automatic computation is a significant achievement. At the same time, new issues were found at the Verilog-A implementation of the vertical non-quasi-static (NQS) effect of bipolar (hetero) junction transistors. It turned out that the well-behaving adjunct network solution of the VBIC model 7 did not provide the expected results in HICUM. 8 It was found that the derivative of the delay time TD related charge element (TD ⋅ V) in the adjunct network produced terms proportional to the derivatives of TD. Such "undesired derivatives" are not present in VBIC since the delay time is constant there as opposed to the bias dependent TD of HICUM. Similar charge expressions can be found in Verilog-A models elsewhere without implying "undesired derivative" issues. It appears inconsistent at first sight. However, it was theoretically proven that in this specific case, the generated surplus derivatives really distorted the result. 9 The problem could be solved by adopting a scaling with t 0 /TD to the adjunct network. It puts a constant t 0 time parameter in the charge terms while relocated TD to the non-energy-storing components. 10 This avoided the generation of the TD derivatives in the charge elements. The method made it possible for the HICUM providers to implement the Weil-McNamee NQS approach 11 in their Verilog-A model code.An alternative scenario could be obtained by leaving TD in its original place but then suppressing its derivatives some way. This would be a sol...

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Section: Case Studiesmentioning

confidence: 99%

Section: Case Studiesmentioning

confidence: 99%

Section: Case Studiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Suppressing derivatives of selected variables in Verilog‐A

Huszka

Molnar

2019

Circuit Theory & Apps

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“…Solving the equations in ( 18) simultaneously for V(X2) gives 𝐼 𝜔 . As pointed out in [26], it is important to note that default convergence tolerance in Verilog-A is 10 -6 for node voltages and 10 -12 for currents, typically. Due to this reason, the assignment of a current to a node voltage while solving for model-intrinsic node variables, as is the case for (18), results in the convergence tolerances mismatched by a factor of 10 6 that might lead to simulation problems.…”

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confidence: 99%

SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design

Mukherjee

Guendouz

Deng

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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Implementation of Delay-Time-Based Nonquasi-Static Bipolar Transistor Models in Circuit Simulators

Huszka

Chakravorty

2014

IEEE Trans. Electron Devices

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Bipolar Transistor Excess Phase Modeling in Verilog-A

Cited by 5 publications

References 8 publications

Suppressing derivatives of selected variables in Verilog‐A

Suppressing derivatives of selected variables in Verilog‐A

SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design

Implementation of Delay-Time-Based Nonquasi-Static Bipolar Transistor Models in Circuit Simulators

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