Bit-level pipelined digit-serial array processors

Abstract

Abstract-A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2 n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure.A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented.

Two-dimensional DCT∕IDCT architecture

“…The radix-2 n VIP algorithm described by equation (8) v are their most significant bits. Following the same procedure as in [10] and [12], the multiplication of two B-bit two's complement numbers, U i and V i , can be written in a form involving only positive partial products provided that all partial products which involve a sign bit and a nonsign bit are complemented. The final product is then obtained by adding a fixed correction term to the final result, viz.,…”

“…The proposed architecture of the vector inner product is derived from a design methodology using radix-2 n arithmetic reported by A. Aggoun et.al. [10]. To demonstrate the proposed methodology, the inner product of the vectors U i = c pi and V i = X ij + (-1) p X (N-1-i)j described by equation 4 is considered.…”

“…To demonstrate the proposed methodology, the inner product of the vectors U i = c pi and V i = X ij + (-1) p X (N-1-i)j described by equation 4 is considered. Using the radix-2 n arithmetic and assuming unsigned numbers, U i can be divided into K digits of n-bit each and can be written as [10],…”

Radix-2n serial–serial multipliers

“…In this paper, an architecture for digit serial-serial multipliers is presented. A set of designs are derived from the radix-2 n design procedure which was first reported by the authors for the design of bit level pipelined digit serial-parallel structures [8].…”

“…In this paper, an architecture for digit serial-serial multipliers is presented. A set of designs are derived from the radix-2 n design procedure which was first reported by the authors for the design of bit level pipelined digit serial-parallel structures [8].One significant aspect of the new designs is that they can be pipelined to the bit level and give the designer the flexibility to obtain the best trade off between throughput rate and hardware cost by varying the digit size and the number of pipelining levels. Also in this paper an area efficient digit serial-serial multiplier is proposed which provides a 50% reduction in hardware without degrading the speed performance.…”