Block-based Schema-driven Assertion Generation for Functional Verification

Hekmatpour, Amir; Salehi, Azadeh

doi:10.1109/ats.2005.30

Cited by 13 publications

(5 citation statements)

References 1 publication

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“…Template-driven assertion generation is one of the earlier attempts to automate assertion generation [59]. Figure 10 gives an overview of the process.…”

Section: Static Analysis Of Specificationmentioning

confidence: 99%

“…[110] analyzes the syntax and extract properties from a RTL design then generate assertions based on the extracted properties. In contrast, it [59], [110] uses model checking for assertion veriication.…”

Section: Static Analysis Of Specificationmentioning

confidence: 99%

“…Finally, the A-Val evaluates and ranks the assertions using support and conidence metric. Similar to [59], GoldMine is a white-box approach. GoldMine tries to avoid incorrect assertion generation using formal veriication.…”

Section: Dynamic Analysis Of Simulation Tracesmentioning

confidence: 99%

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A Survey on Assertion-based Hardware Verification

et al. 2022

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Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements.

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“…Template-driven assertion generation is one of the earlier attempts to automate assertion generation [59]. Figure 10 gives an overview of the process.…”

Section: Static Analysis Of Specificationmentioning

confidence: 99%

Section: Static Analysis Of Specificationmentioning

confidence: 99%

See 1 more Smart Citation

A Survey on Assertion-based Hardware Verification

et al. 2022

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“…In hardware, the techniques in [12] [26] also generate assertions based on structural analysis of designs. Static analysis can generate accurate assertions without spending formal verification time and effort in checking them.…”

Section: Introductionmentioning

confidence: 99%

Generating concise assertions with complete coverage

Lin

Liu

Vasudevan

2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

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Assertions are valuable and commonly applied to formal verification and simulation-based verification in IC design flow. Unfortunately, assertion generation is a time-consuming process that depends heavily on human efforts. Some dynamic methods based on simulation and static methods based on structure analysis are proposed to automate assertion generation process. However, dynamic methods cannot guarantee the quality of assertions due to incomplete simulation while static methods might have scalability limits. With the significant advances in Boolean satisfiability (SAT) solving, SAT solving becomes a promising technique to overcome these methods' weaknesses. In this paper, we successfully formulate assertion generation to a SAT problem and use unit assumption to generate concise assertions. Furthermore, we consider input constraints and word level features to generate meaningful and high-readability assertions. Experimental results on SpaceWire, Ethernet, and Floating Point designs show that the generated assertions can always achieve 100% input space coverage.

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“…In hardware, there have been no prior attempts to generate assertions through data mining and static analysis of RTL source code. Assertion generation in hardware by statically analyzing the hardware structure and topology has been explored before [8]], [ [9]. IODINE [10] infers detailed, low-level dynamic invariants for hardware designs.…”

Section: Introductionmentioning

confidence: 99%

GoldMine: Automatic assertion generation using data mining and static analysis

Vasudevan

Sheridan

Patel

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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We present GOLDMINE, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. We present results of using GoldMine for assertion generation of the RTL of a 1000-core processor design that is still in an evolving stage. Our results show that GoldMine can generate complex, high coverage assertions in RTL, thereby minimizing human effort in this process.

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Block-based Schema-driven Assertion Generation for Functional Verification

Cited by 13 publications

References 1 publication

A Survey on Assertion-based Hardware Verification

A Survey on Assertion-based Hardware Verification

Generating concise assertions with complete coverage

GoldMine: Automatic assertion generation using data mining and static analysis

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