BM-RCGL: Benchmarking Approach for Localization of Reliability-Critical Gates in Combinational Logic Blocks

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

“…The proposed simulation approach has been evaluated in a series of experiments and compared against some representative approximation methods. Considering that 74-series and ISCAS 85 benchmark circuits were widely employed in previous studies, 11,12,14,19 to facilitate comparison with other similar methods, 19,32 based on the NVIDIA CUDA architecture, we conducted all simulations shown in this paper on the benchmark circuits to investigate the performance of the proposed method. The host system contains a Core i5 processor (1.9 GHz) and an 8-GB memory.…”

“…Because they are widely used in medical, military, and flight control systems, paying attention to the reliability of the circuits is the need of the hour 10,11 . To shorten the product development cycle and improve market competitiveness, analyzing and estimating the impact of soft errors on circuit reliability at an early stage of circuit design is a growing need 12–15 . Historically, soft errors have been tackled in the context of memory cells because of the large chip area devoted to caches and the higher vulnerability of SRAM cells in comparison with combinational logic circuits 16 .…”

“…10,11 To shorten the product development cycle and improve market competitiveness, analyzing and estimating the impact of soft errors on circuit reliability at an early stage of circuit design is a growing need. [12][13][14][15] Historically, soft errors have been tackled in the context of memory cells because of the large chip area devoted to caches and the higher vulnerability of SRAM cells in comparison with combinational logic circuits. 16 In the last few years, their negative effect on memory has been kept under control by using protection mechanisms, such as error-correcting codes.…”