Body-Biased Subthreshold Bootstrapped CMOS Driver

Karthikeyan, A.; Mallick, P. S.

doi:10.1142/s0218126619500518

Cited by 5 publications

(1 citation statement)

References 14 publications

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“…Although the dynamic power consumption is significantly reduced by the lower supply voltage, the reduction in drain currents of the transistors increases the delay of the comparator. On the other hand, the deep sub‐micron technologies suffer from high leakage currents, which leads to a higher leakage power consumption [29]. Furthermore, in these technologies, the threshold voltage is not reduced accordingly with the supply voltage reduction, so the reductions in supply voltage and power consumption may result in serious design challenges.…”

Section: Introductionmentioning

confidence: 99%

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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Section: Introductionmentioning

confidence: 99%