Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel

Chen, Che-Wei; Chung, Chia-Jung; Tzeng, Ju-Yuan; Chang, Pang-Sheng; Luo, Guang-Li; Chien, Chao–Hsin

doi:10.1109/led.2013.2291394

Cited by 20 publications

(7 citation statements)

References 9 publications

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“…Zhao et al 28 demonstrated JL Ge pMOSFETs fabricated on an ultrathin GeOI substrate with I on /I off value higher than 10 4 at V DS = −0.01 V. However, the applied back-gate bias condition of V GS = −40 to 40 V is unsuitable for modern nanoscale devices. Chen et al 29 presented body-tied Ge trigate JL pMOSFETs fabricated directly on Si substrates, and the fabricated transistors demonstrated an I on /I off value of approximately 6 × 10 3 at V DS = −0.1 V and V GS = −3 and 0 V; our device was superior (by a factor of approximately 10 5 ). 5a shows the total resistance, R Total , of the three types of S/D devices as a function of the overdrive voltage at V DS = −0.1 V. The R SD of the Type I S/D structure was approximately 7.72 × 10 4 × μm, which was approximately a 4.5-fold reduction relative to that of the Type III structure at V GS − V T = −2.5 V. To further explicitly extract the S/D resistance, simple transistor method 30 was used for avoiding several disputed assumptions by "L-array" extraction.…”

Section: Resultsmentioning

confidence: 68%

Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D

Lee¹,

Hsu²,

Chung³

et al. 2017

ECS J. Solid State Sci. Technol.

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We fabricated a Ge junctionless p-channel metal–oxide–semiconductor field-effect transistor (JL pMOSFET) with a raised metal source/drain (S/D) composed of a metal alloy. An ultrathin-body Ge channel was trimmed to 10 nm, which is lower than the maximum depletion width, to completely switch off the device. The fabricated Ge JL pMOSFET containing a raised Ni/NiGe S/D exhibited a high on/off current ratio (Ion/Ioff) value (approximately 105 at VDS = −0.1 V). The S/D series resistance of the full metal S/D structure was exactly lower than the structures of Ge/NiGe and Ge bulk S/D. Synopsys Technology Computer-Aided Design tools were used to confirm the advantages of the full metal S/D structure and demonstrate the enhancement of the S/D resistance in a device with scaled gate length. The proposed scheme is suitable for reducing the series resistance of a device with minimized dimensions.

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Section: Resultsmentioning

confidence: 68%

Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D

Lee¹,

Hsu²,

Chung³

et al. 2017

ECS J. Solid State Sci. Technol.

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“…As compared to the INV Ge GAA pFETs with 52-nm W fin and N ch = 1×10 16 cm -3 [4], JL devices have small SS (95 vs. 130 mV/dec), and large on/off ratio (1.5×10 6 vs. 10 5 ) due to the elimination of junction leakage. Since the defects near Ge/Si has been removed and the effectively gate control of GAA structure, our devices also show better electrostatic performance (95 vs. 203 mV/dec) as compared to the reported JL devices using the bodytied tri-gate structure [20]. The output characteristic exhibits saturation current of 194A/m at at V GS -V T = -2V and V DS = -1 V (Fig.…”

Section: Characterization Of Junctionless Gaa Pfetsmentioning

confidence: 74%

(Invited) Gate-All-Around Ge FETs

Chen

Hsu

2014

ECS Trans.

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High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced Ion of 110 mA/mm at 1V with respect to the devices with near (110) sidewalls and subthreshold characteristics of 94 mV/dec. The JL Ge GAA pFETs with fin width (Wfin) down to 27 nm and channel concentration (Nch) of 5×1018 cm-3 has Ion/Ioff = 1.5×106, SS = 95 mV/dec, and Ion = 194 mA/mm at VGS - VT = -2V and VDS = -1 V.

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“…Furthermore, JL-FETs have the advantages of being simple to fabricate and have high charge mobility and low gate capacitance, in contrast to INV devices [ 8 – 12 ]. Recently, double-gate [ 13 ] and body-tied tri-gate [ 14 ] Ge JL-FET pMOSFETs were demonstrated on germanium-on-insulator substrates and bulk Si, respectively.…”

Section: Introductionmentioning

confidence: 99%

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

2018

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During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile. If the etching process is not well controlled, the top Ge/SOI structure is etched away, and only the Si fin layer remains. In this case, the device exhibits abnormal characteristics. The etching process is emerging as a critical step in device scaling and packaging and affects attempts to increase the packing density and improve device performance. Therefore, it is suggested that optimization of operating the plasma reactor be performed through simulations, in order to not only adjust the process parameters used but also to modify the hardware employed. We are going to develop Ge junction-less devices by employing updated fabrication parameters. Besides, we want to eliminate misfit dislocations at the interface or to reduce threading dislocations by applying cyclic thermal annealing process to meet the goal of obtaining suspended structure of epitaxial Ge layers with high quality.

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Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel

Cited by 20 publications

References 9 publications

Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D

Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D

(Invited) Gate-All-Around Ge FETs

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

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