Boolector 2.0

Niemetz, Aina; Preiner, Mathias; Biere, Armin

doi:10.3233/sat190101

Cited by 100 publications

(43 citation statements)

References 5 publications

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“…6 and any witness for the dual satisfiability question constitutes an adversarial attack. We checked the robustness of our selected networks over the first 300 test samples from the dataset with ε = 1 on the first 200 and ε = 2 on the next 100; in particular, we tested our encoding using the SMT-solver Boolector [19], Z3 [5], and CVC4 [3], off-the-shelf.…”

Section: Resultsmentioning

confidence: 99%

“…As a result, we obtain a encoding into a first-order logic formula which, in contrast to a standard unbalanced linear encoding, makes the verification of quantized networks practical and amenable to modern bit-precise SMT-solving. We built a tool using Boolector [19], evaluated the performance of our encoding, compared its effectiveness against real-numbered verification and gradient descent for quantized networks, and finally assessed the effect of quantization for different networks and verification questions.…”

Section: Introductionmentioning

confidence: 99%

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How Many Bits Does it Take to Quantize Your Neural Network?

Giacobbe

Henzinger

Lechner

2020

Lecture Notes in Computer Science

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Quantization converts neural networks into low-bit fixed-point computations which can be carried out by efficient integer-only hardware, and is standard practice for the deployment of neural networks on real-time embedded devices. However, like their real-numbered counterpart, quantized networks are not immune to malicious misclassification caused by adversarial attacks. We investigate how quantization affects a network’s robustness to adversarial attacks, which is a formal verification question. We show that neither robustness nor non-robustness are monotonic with changing the number of bits for the representation and, also, neither are preserved by quantization from a real-numbered network. For this reason, we introduce a verification method for quantized neural networks which, using SMT solving over bit-vectors, accounts for their exact, bit-precise semantics. We built a tool and analyzed the effect of quantization on a classifier for the MNIST dataset. We demonstrate that, compared to our method, existing methods for the analysis of real-numbered networks often derive false conclusions about their quantizations, both when determining robustness and when detecting attacks, and that existing methods for quantized networks often miss attacks. Furthermore, we applied our method beyond robustness, showing how the number of bits in quantization enlarges the gender bias of a predictor for students’ grades.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

How Many Bits Does it Take to Quantize Your Neural Network?

Giacobbe

Henzinger

Lechner

2020

Lecture Notes in Computer Science

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“…SMT solver backends use the latest versions of state-of-the-art SMT solvers (Yices 2 [30], Boolector [50], MathSAT 5 [24] and Z3 [48]) to efficiently integrate incremental solver reasoning with AVR core using a C++ interface.…”

Section: Motivationmentioning

confidence: 99%

AVR: Abstractly Verifying Reachability

Goel

Sakallah

2020

Lecture Notes in Computer Science

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We present AVR, a pushbutton model checker for verifying state transition systems directly at the source-code level. AVR uses information embedded in the word-level syntax of the design representation to automatically perform scalable model checking by combining a novel syntax-guided abstraction-refinement technique with a word-level implementation of the IC3 algorithm. AVR provides independently-verifiable certificates that offer provable assurance and are easy to relate to the word-level system. Moreover, proof certificates can be further used in innovative ways to extract key design information and are useful in a growing number of applications.

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“…into a DPLL-style SAT decision procedure [27]. Some of the most effective SMT solvers, potentially applicable to our problem, are Boolector [28], Z3 [29], and CVC [30]. However, SMT solvers still model functional verification as a decision problem and, as demonstrated by extensive experimental results, neither SAT nor SMT solvers can efficiently solve the verification problem of large arithmetic circuits [1] [10].…”

Section: B Sat Ilp and Smt Solversmentioning

confidence: 99%

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

Ciesielski

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Galois field (GF) arithmetic circuits find numerous applications in communications, signal processing, and security engineering. Formal verification techniques of GF circuits are scarce and limited to circuits with known bit positions of the primary inputs and outputs. They also require knowledge of the irreducible polynomial P (x), which affects final hardware implementation. This paper presents a computer algebra technique that performs verification and reverse engineering of GF(2 m ) multipliers directly from the gate-level implementation. The approach is based on extracting a unique irreducible polynomial in a parallel fashion and proceeds in three steps: 1) determine the bit position of the output bits; 2) determine the bit position of the input bits; and 3) extract the irreducible polynomial used in the design. We demonstrate that this method is able to reverse engineer GF(2 m ) multipliers in m threads. Experiments performed on synthesized Mastrovito and Montgomery multipliers with different P (x), including NIST-recommended polynomials, demonstrate high efficiency of the proposed method.

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Boolector 2.0

Cited by 100 publications

References 5 publications

How Many Bits Does it Take to Quantize Your Neural Network?

How Many Bits Does it Take to Quantize Your Neural Network?

AVR: Abstractly Verifying Reachability

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

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