Recently, various two-dimensional (2D) materials, such as graphene, transition metal dichalcogenides and so on, have attracted much attention in electron device research. The most important characteristic of graphene is its highest mobility of all semiconductor channels at room temperature. However, it is obvious that more than a good mobility characteristic is required to realize the field effect transistor (FET), and intense arguments from various points of view are necessary. In this paper, the issues with Si-metal oxide semiconductor FETs (Si-MOSFET) and the advantage of 2D materials are discussed. The present state of graphene FETs with respect to gate stack formation and band gap engineering is reported. Moreover, based on the density of states (DOS) of graphene extracted using the quantum capacitance (C Q ) measurement, it is shown that the electric band structure of graphene in contact with gate insulators or metal electrode deviates from its intrinsic band structure.
I. ISSUES WITH Si-MOSFET AND THE ADVANTAGE OF 2D CHANNELSThe issues with the miniaturization of Si-MOSFETs are generically called short channel effects.1 When the source and drain depletion regions become comparable in length with the channel length, as shown in Fig. 1(a), the drain bias weakens the gate bias, which leads to a drastic increase in the off-current. Based on an analysis of the distribution of the electrical potential in the channel region, it is widely known that the short channel effect can be neglected when the channel length is ;6 times longer than the scaling length, k ¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi e ch t ch t ox ð Þ = Ne ox ð Þ p , 2,3 where e ch , e ox , t ch , and t ox are the dielectric constants for the channel, the gate insulator, the thickness of the channel, and the gate oxide, respectively. Figure 1(b) shows the 6k values calculated for Si, carbon nanotubes (CNT), bilayer graphene, and MoS 2 , where the contribution of the tunneling effect is neglected. N is defined as the effective gate number: N 5 1 for planar, N 5 2 for dual gate, N 5 3 for FIN-FET, and N 5 4 for gate-all-around. Although the FIN structure has already been adopted for Si to reduce the short channel effects, 4 it is difficult to avoid the short channel effects for channel lengths shorter than 10 nm. 2D layered channels in FET applications are attractive because of their rigidly controllable atomic thickness (t ch , 1 nm) and their low dielectric constants where e ch 5 ;4 for a typical 2D layered channel. 3,4 This results in a 6k smaller than that of Si. Of course, Si channels of a few nanometers thick have already been constructed using the microfabrication process. However, the operation of Si-MOSFET with an atomic scale thickness is not realistic because the mobility is drastically reduced because of fabrication damage. 5,6 The advantage of 2D materials is their intrinsic atomic thickness, 7,8 which allows both the reduction of the short channel effect and