Bounded Model Debugging

Abstract

Abstract-Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical design blocks exceeding half a million synthesized logic gates and error traces in the thousands of clock cycles, the complexity of the debugging problem poses a great challenge to automated debugging techniques. This work aims to address this daunting challenge by introducing the Bounded Model Debugging methodology that iteratively analyzes bounded sequences of the error trace. Two techniques are introduced in this methodology to solve this growing problem. The first technique iteratively analyzes bounded subsequences of the error trace of increasing size until the error is found or the entire trace is analyzed. The second technique partitions the error trace into non-overlapping bounded sequences of clock cycles which are each separately analyzed. A discussion of these two techniques is presented and a unified methodology that leverages the strengths of both techniques is developed. Empirical results on real industrial designs show that for large designs and long error traces the proposed methodology can find the actual error in 79% of cases with the first technique and 100% of cases with the second technique. In cases where the methodology is not used only 21% of cases are able to find the actual error. These numbers confirm the benefits of the proposed methodology to allow conventional automated debuggers to handle much larger real-life circuits.

From RTL to silicon: The case for automated debug

“…Whether using a manual or an automatic approach, the debugging problem becomes more complex as the design, error trace length and the number of errors grow [6]:…”

“…By leveraging the tremendous amount of research in formal verification, recent advances [6], [17], [18] have been able to further contain much of the parameters behind the inherent complexity (Equation 1) in design debugging. The most promising techniques manage the design size and the error trace length.…”

“…Bounded Model Debugging [6] works by analyzing subsections, or windows, of the error trace. In this debugging-independent formulation, the algorithm iteratively models a growing suffix window of the error trace.…”

Path directed abstraction and refinement in SAT-based design debugging

“…Abstraction and refinement techniques [7,10] have shown to greatly reduce the effective design size by iteratively refining the abstract design until a minimal set of necessary components are determined. Orthogonally, time-windowing techniques [6,13] use a sliding window of consecutive clock cycles to analyze the problem. In this fashion, they model only a segment of the entire error trace and they use different methods to approximate the remaining non-modeled parts.…”

“…The algorithm is also shown to be complete in contrast to previous approximate time-windowing methods that provide no means of refinement [6]. The process begins by dividing the error trace into non-overlapping time-windows where each window is analyzed separately.…”