Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture

Danial, Loai; Wainstein, Nicolás; Kraus, S.; Kvatinsky, Shahar

doi:10.1109/tetci.2018.2849109

Cited by 48 publications

(19 citation statements)

References 44 publications

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“…Such hardware networks, commonly referred to as neuromorphic electronic systems [33], implement configurable DNNs as analog components. Recent advances in memristors technology substantially facilitate the implementation of these hardware devices [39], contributing to the feasibility of our proposed deep task-based quantizer.…”

Section: Discussionmentioning

confidence: 99%

Hardware-Limited Task-Based Quantization

Shlezinger

Eldar

Rodrigues

2019

IEEE Trans. Signal Process.

108

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Quantizers play a critical role in digital signal processing systems. Recent works have shown that the performance of quantization systems acquiring multiple analog signals using scalar analog-to-digital converters (ADCs) can be significantly improved by properly processing the analog signals prior to quantization. However, the design of such hybrid quantizers is quite complex, and their implementation requires complete knowledge of the statistical model of the analog signal, which may not be available in practice. In this work we design data-driven task-oriented quantization systems with scalar ADCs, which determine how to map an analog signal into its digital representation using deep learning tools.These representations are designed to facilitate the task of recovering underlying information from the quantized signals, which can be a set of parameters to estimate, or alternatively, a classification task. By utilizing deep learning, we circumvent the need to explicitly recover the system model and to find the proper quantization rule for it. Our main target application is multiple-input multiple-output (MIMO) communication receivers, which simultaneously acquire a set of analog signals, and are commonly subject to constraints on the number of bits. Our results indicate that, in a MIMO channel estimation setup, the proposed deep task-bask quantizer is capable of approaching the optimal performance limits dictated by indirect rate-distortion theory, achievable using vector quantizers and requiring complete knowledge of the underlying statistical model. Furthermore, for a symbol detection scenario, it is demonstrated that the proposed approach can realize reliable bit-efficient hybrid MIMO receivers capable of setting their quantization rule in light of the task, e.g., to minimize the bit error rate.

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Section: Discussionmentioning

confidence: 99%

Hardware-Limited Task-Based Quantization

Shlezinger

Eldar

Rodrigues

2019

IEEE Trans. Signal Process.

108

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“…61 ), useful for a variety of intracellular and extracellular biosensing applications. The conversion of analog information into digital encoding is a classification problem that is efficiently solved by ANN architectures 62 ( Supplementary Notes , Design and implementation of 2-bit log-ADC). We evaluated three designs, starting from a perceptgene adaptation of a classical ADC perceptron network 62 , a second design that adds two inhibitory regulatory links, and a third design that improves the fidelity of the digital output signals.…”

Section: Resultsmentioning

confidence: 99%

Synthetic neuromorphic computing in living cells

et al. 2022

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Computational properties of neuronal networks have been applied to computing systems using simplified models comprising repeated connected nodes, e.g., perceptrons, with decision-making capabilities and flexible weighted links. Analogously to their revolutionary impact on computing, neuro-inspired models can transform synthetic gene circuit design in a manner that is reliable, efficient in resource utilization, and readily reconfigurable for different tasks. To this end, we introduce the perceptgene, a perceptron that computes in the logarithmic domain, which enables efficient implementation of artificial neural networks in Escherichia coli cells. We successfully modify perceptgene parameters to create devices that encode a minimum, maximum, and average of analog inputs. With these devices, we create multi-layer perceptgene circuits that compute a soft majority function, perform an analog-to-digital conversion, and implement a ternary switch. We also create a programmable perceptgene circuit whose computation can be modified from OR to AND logic using small molecule induction. Finally, we show that our approach enables circuit optimization via artificial intelligence algorithms.

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“…[ 22,23 ] Meanwhile, other research started with a verified CAD model which was then utilized to fabricate an FGT in a standard 180 nm CMOS process. [ 10,27 ]…”

Section: Introductionmentioning

confidence: 99%

“…[22,23] Meanwhile, other research started with a verified CAD model which was then utilized to fabricate an FGT in a standard 180 nm CMOS process. [10,27] The reported effective voltage range for charge tunneling in MOSFETs with 20 and 7 nm dielectric is between 1.2 and 5 V for transistors fabricated with 0.25 and 0.18 µm CMOS processes. [26] The thinner the dielectric layer is, the trickier it becomes reliably and controllably tunnel charges through it, because of the high sensitivity of the tunneling mechanism to the applied voltage.…”

Section: Introductionmentioning

confidence: 99%

A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

Assaf

Savaria

Ali

et al. 2023

Adv Elect Materials

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of programmable devices are retention time, conductanceoperating voltage range, device dimensions, and robustness. [3] The memristor, which is considered the fourth circuit element, [4] is a good example of a programmable resistor. [5,6] Along with other resistive devices, memristors have been integrated into several domains such as: a) computing including in-memory computing, near-memory computing, and resistive computing with crossbar arrays, b) data storage including both passive and active types corresponding to long-term and short-term data retention times, respectively, and c) other domains such as logic-gate realizations and radio-frequency switches.However, due to challenges faced with memristor fabrication, these nano-devices are often replaced by emulating circuits fabricated using a standard CMOS process. [7] Although many memristor emulators have circuit responses close to that of the actual device, they still lack the potential to trap charges for long periods of time, a problem that is commonly solved using charge traps (CTs). A CT is a circuit branch designed to prolong the circuit's retention time, and in most designs, it is implemented using floating gate transistors (FGTs) which have been demonstrated in 1971. [8] FGTs were utilized in various applications that need non-volatile analog memories as in electrically erasable programmable read only memories (EEPROMs). [9] They have also become an integral part of analog computing engines that depend on crossbar arrays, replacing the tiny resistive devices in these structures. [10] Moreover, FGTs were used in programmable analog solvers like field programmable analog arrays (FPAAs), which add flexibility to analog-based circuit solutions. [11,12] Some CTs (an FGT trap, for example) can trap charges for long periods of time (up to 10 years). This characteristic is often referred to as retention time. The underlying CMOS process has a direct effect on this characteristic. Not only are CTs characterized by their retention times, but also by other features that contribute to giving each CT a unique identity. Some of these features which directly relate to FGTs are: a) the transistor dimensions, length and width, which affect the tunneled current and induce more parasitic capacitance in a cell; b) the dielectric thickness which has a direct effect on charge tunneling; c) the charging capacity, and d) the discharging

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Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture

Cited by 48 publications

References 44 publications

Hardware-Limited Task-Based Quantization

Hardware-Limited Task-Based Quantization

Synthetic neuromorphic computing in living cells

A Memristive Cell with Long Retention Time in 65 nm CMOS Technology

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