Breakthroughs in 3D Sequential technology

Brunet, Laurent; Fenouillet-Béranger, C.; Batude, P.; Beaurepaire, S.; Ponthenier, F.; Rambal, N.; Mazzocchi, V.; Pin, J-B.; Acosta-Alba, P.; Kerdilès, S.; Besson, P.; Fontaine, Hervé; Lardin, T.; Fournel, Frank; Larrey, Vincent; Mazen, F.; Balan, V.; Morales, Christophe; Guérin, C.; Jousseaume, V.; Federspiel, X.; Ney, D.; Garros, X.; Roman, A.; Scevola, Daniel; Perreau, P.; Kouemeni-Tchouake, F.; Arnaud, L.; Scibetta, C.; Chevalliez, S.; Aussenac, F.; Aubin, J.; Reboh, S.; Andrieu, F.; Maîtrejean, S.; Vinet, M.

doi:10.1109/iedm.2018.8614653

Cited by 42 publications

(25 citation statements)

References 2 publications

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“…Since monolithic 3D enables the finest pitch of 3D connection, it holds the most promise. However, more breakthroughs in low-temperature processing to fabricate transistors in the upper layers while preserving the transistors and Back end of line (BEOL) of the lower layer are desired [29]. Monolithic 3D suffers from limited lateral thermal conductivity due to the absence of substrate on upper layers.…”

Section: A Overview Of 3d Integration Technologiesmentioning

confidence: 99%

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Mathur

Kumar

John

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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ML accelerators have a broad spectrum of usecases that pose different requirements on accelerator design for latency, energy, and area. In the case of systolic array-based ML accelerators, this puts different constraints on Processing Element (PE) array dimensions and SRAM buffer sizes. 3D integration packs more compute or memory in the same 2D footprint, which can be utilized to build more powerful or energyefficient accelerators. However, 3D also expands the design space of ML accelerators by additionally including different possible ways of partitioning the PE array and SRAM buffers among the vertical tiers. Moreover, the partitioning approach may also have different thermal implications. This work provides a systematic framework for performing system-level design space exploration of 3D systolic accelerators. Using this framework, different 3D-partitioned accelerator configurations are proposed and evaluated. The 3D-stacked accelerator designs are modeled using hybrid wafer bonding technique with a 1.44 µm pitch of 3D connection. Results show that different partitioning of the systolic array and SRAM buffers in a 4-tier 3D configuration can lead to either 1.1-3.9X latency reduction or 1-3X energy reduction compared to the baseline design of the same 2D area footprint. It is also shown that by carefully organizing the systolic array and SRAM tiers using logic over memory, the temperature rise with 3D across benchmarks can be limited to 6°C.

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Section: A Overview Of 3d Integration Technologiesmentioning

confidence: 99%

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Mathur

Kumar

John

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…wafer bonding technique. Stacked NWs [16][17][18][19], Si nanosheets [18,20], 3D SI CMOS [51,[21][22][23] are widely discussed to boost the device performance.…”

Section: Introductionmentioning

confidence: 99%

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Kilchytska

Makovejev²,

Esfeh

et al. 2021

IEEE J. Electron Devices Soc.

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This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as Fully Depleted Silicon-on-Insulator (FDSOI), FinFETs and NanoWires (NW) in a wide temperature range (from cryogenic, 4 K up to 250°C). A wide frequency band characterization (from DC up to hundred GHz range) will be positioned as a key element enabling a fair device assessment towards analog and RF applications. Importance of the "extrinsic" parasitic elements in the advanced devices is enormous, sometimes even dominating the device performance. Therefrom arises the need for a proper separate extraction and discussion of "intrinsic" versus "extrinsic" parameters.

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“…In addition, this integration scheme offers a wide spectrum of applications including (i) increasing integration density beyond device scaling, (ii) enabling neuromorphic integration where RRAM is placed between top and bottom tiers, and (iii) enabling low-cost heterogeneous integration for e.g., smart sensing arrays. However, such an integration process faces the challenges of fabricating high-performance devices in the top tier without degrading the electrical characteristics of the bottom tier [18,19].…”

Section: Introductionmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Breakthroughs in 3D Sequential technology

Cited by 42 publications

References 2 publications

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Miniaturization of CMOS

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