Bridging defects resistance in the metal layer of a CMOS process

Abstract

The resistance value of bridging defects in CMOS VLSI circuits are evaluated through a set of measurements performed on process-related defect monitoring wafers. The monitor circuits considered are made of metall lines. The results show how the vast majority of the measured metall to metall bridges has a low resistance. Only a small percentage of the overall bridges resulted in a resistance value above 500 f2, while the exact percentage can vary from batch to batch. This high resistance does not seem to be the result of the material of the defect itself, since all these bridging defects were found to be caused by extra aluminium. The shape and location of the defect seem to be the cause of the high resistance values probably caused by poor contacts between the extra metal and the designed monitor lines.

High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations

“…We consider single resistive non-feedback BFs whose resistance (Ê) can be varied in a wide range [7] inside simple circuits because, in the considered case, the effects of parameters fluctuations are mainly local (this does not hold for faster test rates), regarding the electrical behavior of the directly involved gates and a few levels of gates in their transitive fan-out. The considered circuits are, then, representative of subcircuits embedded in larger combinational blocks.…”