Built-in jitter measurement circuit for PLL based on variable vernier delay line

Abstract

In this paper, a novel built-in jitter measurement circuit (BIJM) for Phase-Locked Loops (PLL) based on a variable vernier delay line (VVDL) is proposed. Resolutions of the two-level VDLs can be designed flexibly and their lengths optimally according to the signal under test (SUT).A digitally controlled delay element (DCDE) using varactors acts as the basic delay element in VVDL. Instead of counters, thermometer-to-binary encoders are adopted in the design. An improved phase detector (PD) is also introduced. The circuit has been designed using an all-digital design methodology and verified with the TSMC 130 nm CMOS process. 800 MHz clock frequency is chosen, and the circuit occupies a total silicon area of 0.043 mm 2 , which is reduced by 60% compared to the traditional VDL.Simulation results indicate coarse timing resolution of 15.4 ps and fine resolution of 2.1 ps, and measurement error is within 2.11%.