An all-digital circuit for on-chip measuring the long-term jitter of Phase-Locked Loop (PLL) using the undersampling technique is presented in this paper. The circuit comprises the undersampling circuit, which samples the PLL output signal and the data analysis circuit, which calculates the statistical value of the jitter. The data statistics approach is based on accumulating data from multiple edge regions with cycle edge alignment, which is suitable for measuring the long-term jitter of PLL clock signal. The proposed built-in self-test (BIST) circuit can test the PLL output signal whose frequency is greater than 1 GHz. And it can provide high measurement resolution that is up to 1 ps. The circuit was designed in Verilog, and fabricated in TSMC 130 nm CMOS process. Simulated results show the possibility of detecting 45 ps RMS long-term jitter of a 1 GHz clock with less than 2% error.

In this paper, a hybrid built-in self-test (BIST) scheme is firstly proposed for phase-locked loop (PLL) production test and performance characterization. The scheme combines the structure test and function test in production test operation. The former is to detect hard faults and the latter is used to improve the soft fault coverage. Jitter measurement is selected as a typical parameter test in performance characterization mode, which includes vernier delay line (VDL) to measure timing jitter and undersampling technology to measure cycle-cycle jitter. The goal of the scheme is to enable complete production quality test and exact performance characterization.

An improved BIJM (Built-in jitter measurement) circuit is presented in this paper, which is consisted of three improvement points. Firstly, multi-phase sampling technology improves the sampling efficiency based on the specially designed multi-phase clock generation circuit. Secondly, the median-edge alignment is used as the new jitter extraction method, which is taking the place of the mean-edge alignment. This method can filter lowfrequency noise component to extract the cycle-to-cycle jitter. Thirdly, single-edge accumulation data processing method accumulates one edge in each cycle, blocking the correlation of adjacent sampling location, which can improve measurement accuracy and save the area overhead. The proposed jitter measurement circuit is designed at SMIC 40 nm CMOS process, and the circuit occupies a total silicon area of 9108 um 2 . Post-layout simulation results show the measurement error is only 0.94%.

In this paper, a novel built-in jitter measurement circuit (BIJM) for Phase-Locked Loops (PLL) based on a variable vernier delay line (VVDL) is proposed. Resolutions of the two-level VDLs can be designed flexibly and their lengths optimally according to the signal under test (SUT).A digitally controlled delay element (DCDE) using varactors acts as the basic delay element in VVDL. Instead of counters, thermometer-to-binary encoders are adopted in the design. An improved phase detector (PD) is also introduced. The circuit has been designed using an all-digital design methodology and verified with the TSMC 130 nm CMOS process. 800 MHz clock frequency is chosen, and the circuit occupies a total silicon area of 0.043 mm 2 , which is reduced by 60% compared to the traditional VDL.Simulation results indicate coarse timing resolution of 15.4 ps and fine resolution of 2.1 ps, and measurement error is within 2.11%.