Built‐in self‐test structure for fault detection of charge‐pump phase‐locked loop

Abstract

A defect-oriented built-in self-test (BIST) structure of charge-pump phase-locked loop (CP-PLL) for high fault coverage and low area overhead test solution is proposed. It employs a new structure of phase/frequency detector, a D flip-flop and some existing blocks in the PLL as the input stimulus generator and fault feature extracted devices for testing evaluation. Thus, no extra test stimulus or high-performance measured instruments are required for test. The structure is easily implemented and has a little influence on the performance of CP-PLL. Fault simulation results indicate that the proposed BIST structure has high fault coverage (98.75%) and low area overhead (0.78%).

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

“…A widely accepted structural fault model of PLL [19][20][21][22] has been built to evaluate the fault coverage of proposed BIST scheme on low-cost production test of CP-PLL. As shown in Table 1, the structural fault types include the following: Gate-todrain short (GDS), Gate-to-source short (GSS) For each test, different single known faults will be preset in the CUT.…”

“…A widely accepted structural fault model of PLL [19–22] has been built to evaluate the fault coverage of proposed BIST scheme on low‐cost production test of CP‐PLL. As shown in Table 1, the structural fault types include the following: Gate‐to‐drain short (GDS), Gate‐to‐source short (GSS), Gate‐open (GO), Drain‐to‐source short (DSS), Capacitance‐short (CS), Source‐open (SO), Drain‐open (DO), Resistor‐short (RS) and Resistor‐open (RO).…”

“…It shows high fault coverage, but only focussed on voltage controlled oscillator (VCO) testing. The approaches adopted in [18][19][20][21][22], which have made further modifications of previous BIST structure, provide valuable basis for the low-cost all-digital strategy of CP-PLL testing. However, in most of these improved structures, there are too many external clocks introduced during testing, which increase the I/O ports needed for test.…”

“…Many different structures of time‐to‐digital converter have been used in the method, such as that based on the delay line, the Vernier ring oscillator, and the time‐to‐voltage converter. Though it achieves a very excellent time resolution, the additional test circuits are usually too complex with high area overhead. Defect‐oriented test (DOT) [15–22]. …”

“…It shows high fault coverage, but only focussed on voltage controlled oscillator (VCO) testing. The approaches adopted in [18][19][20][21][22],…”