C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

Jiang, Zhewei; Yin, Shihui; Seo, Jae-sun; Seok, Mingoo

doi:10.1109/jssc.2020.2992886

Cited by 212 publications

(86 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To adequately reflect the additional computational complexity tackled by multibit accelerators, the respective quantization of weight n w and input n x can be factored in, similar to the approach taken in [19], yielding precision scaled TOP/s and TOP/s/W. This is shown in Table III, where recent implementations of analog in-memory MAC-operation accelerators using SRAM combined with capacitors [17], [18], [30], [31] are compared with the presented work.…”

Section: System Implementation Study and Analysismentioning

confidence: 99%

“…Both the accelerator systems presented in [17] and [31] demonstrate high parallelism with completely binary implementations for inputs and weights. Note that, in binary cases, a multiply operation can be reduced to a single XNOR opera-tion [32].…”

Section: System Implementation Study and Analysismentioning

confidence: 99%

“…In addition to the pure analog IMC approaches listed in Table III, a very interesting combination of a binary IMC approach with digital techniques to increase precision was presented in [33]. Specifically, through the use of digital shift and add circuitry, binary-only analog accelerators as, for example, in [31] and [17], can gain linear scalability in terms of weight and input quantizations. However, this incurs a cost in terms of latency and energy due to the multiple ADC cycles, as well as an increase in the area due to the peripheral digital adder circuits.…”

Section: System Implementation Study and Analysismentioning

confidence: 99%

See 2 more Smart Citations

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Khaddam-Aljameh

Francese

Benini

et al. 2021

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Section: System Implementation Study and Analysismentioning

confidence: 99%

Section: System Implementation Study and Analysismentioning

confidence: 99%

Section: System Implementation Study and Analysismentioning

confidence: 99%

See 1 more Smart Citation

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Khaddam-Aljameh

Francese

Benini

et al. 2021

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

“…On the other hand, the compute-in-memory (CiM) technology significantly reduces the latency and energy of the data movements compared to the von Neumann architecture, by enabling computations in the memory array. Recently, several researchers implemented XAC on CiM SRAMs by adding additional transistors to the conventional 6T SRAM for BNN [3,[5][6][7]. However, though such CiM SRAMs reduce the latency and energy of the data movements, the CiM SRAMs with the 2D planar structure suffer from the large cell area overhead (e.g., a 12T CiM SRAM has 2.7× larger cell area than the 6 T SRAM [3]), due to the additional transistors.…”

Section: Introductionmentioning

confidence: 99%

A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM

2021

View full text Add to dashboard Cite

Binary neural networks (BNNs) are adequate for energy-constrained embedded systems thanks to binarized parameters. Several researchers have proposed the compute-in-memory (CiM) SRAMs for XNOR-and-accumulation computations (XACs) in BNNs by adding additional transistors to the conventional 6T SRAM, which reduce the latency and energy of the data movements. However, due to the additional transistors, the CiM SRAMs suffer from larger area and longer wires than the conventional 6T SRAMs. Meanwhile, monolithic 3D (M3D) integration enables fine-grained 3D integration, reducing the 2D wire length in small functional units. In this paper, we propose a BNN accelerator (BNN_Accel), composed of a 9T CiM SRAM (CiM_SRAM), input buffer, and global periphery logic, to execute the computations in the binarized convolution layers of BNNs. We also propose CiM_SRAM with the subarray-level M3D integration (as well as the transistor-level M3D integration), which reduces the wire latency and energy compared to the 2D planar CiM_SRAM. Across the binarized convolution layers, our simulation results show that BNN_Accel with the 4-layer CiM_SRAM reduces the average execution time and energy by 39.9% and 23.2%, respectively, compared to BNN_Accel with the 2D planar CiM_SRAM.

show abstract

“…Recently, various types of CIM architectures have been investigated using memory cells as a synaptic device for weighted sum or vector-matrix multiplication (VMM). CIM accelerators based on the mainstream device technologies such as SRAM [3][4], NOR Flash [5] and NAND Flash [6][7][8][9] have been proposed and verified in silicon. Furthermore, the emerging nonvolatile (NVM) memories such as RRAM [10][11][12][13][14][15] and PCM [16][17] have been considered as strong candidates due to the multilevel capability (over SRAM) and lower programming voltage (over Flash).…”

Section: Introductionmentioning

confidence: 99%

Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Shim

2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

Different from the deep neural network (DNN) inference process, the training process produces huge amount of intermediate data to compute the new weights of the network. Generally, on-chip global buffer (e.g. SRAM cache) has limited capacity because of its low memory density, therefore the off-chip DRAM access is inevitable during the training sequences. In this work, a novel ferroelectric field effect transistor (FeFET) based 3D NAND architecture for on-chip training accelerator is proposed. The reduced peripheral circuit overheads owing to the low operation voltage of FeFET device and ultra-high density of 3D NAND architecture enables storing and computing all the intermediate data on chip during the training process. We present a custom design of 108 Gb chip with 59.91 mm 2 area with 45 % array efficiency. The relevant data mapping schemes for weights/activations/errors that are compatible to the 3D NAND architecture are investigated. The training performance was explored while ResNet-18 model is trained on this architecture with ImageNet dataset by 8-bit precision. Thanks to the minimized off-chip memory access, 7.76 TOPS/W of energy efficiency was achieved for 8-bit on-chip training.

show abstract

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

Cited by 212 publications

References 30 publications

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM

Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Contact Info

Product

Resources

About