C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Abstract

Controlled Collapse Chip Connection -New Process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300mm Pb-free solder bumped wafers. Both 200 µm and 150 µm pitch products have been qualified and are currently ramping up volume production.Extendibility of C4NP to 50 µm ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.

Environment versus sustainable energy: The case of lead halide perovskite-based solar cells

“…Notably, novel research allows companies to release state-of-the-art RoHS conforming products that are currently exempt from compliance, e.g., the lead-free packaging technology announced by IBM as a solution for high lead solder joints. 105 Currently, a few tens of exemptions exist with a lifetime ranging from five to seven years. Since RoHS 2 taking effect, exemptions for which no application of renewal is submitted in due time will expire on the date specified in the RoHS article 5 or in RoHS annexes.…”

Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

“…Therefore, manufacturing of fine-pitch C4 (i.e., controlled-collapse-chipconnection, 50 m) interconnects is required for fine-pitch area interconnects in 3D packaging. Previous work pointed out that C4 new process (C4NP) for Pb-free bumping technology can be extendable to fine-pitch applications for volume production at low cost compared with evaporation, paste screening, electroplating and the direct attach of preformed solder spheres solder bumping technologies [2]. It has been shown that the diameter of microbumps is about 20-10 m in TSV technology for 3D IC, and the density is about 10 5 -10 6 joints/cm 2 (i.e., interconnects/cm 2 ) [3].…”

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

“…Various interconnection types with different materials, sizes, and even structures have been reported in recent years. Common interconnection structures such as microbumps and Cu pillars have been used in 3D chip-stacking structures [13][14][15][16][17][18][19][20][21][22]. Generally, the trend of the interconnection is becoming smaller in dimension, finer in pitch, and higher in interconnection density.…”

“…Different methods of making C4 bumps, such as masked evaporation [37], paste screening [38], and photolithographic electroplating [39], have been developed since its invention. A current C4 bumping technology developed by IBM, the C4-New Process (C4NP), has already been used in 3D chip-stacking [21,22,40]. The C4NP process utilizes a glass mold with cavities to transfer solder to the wafer.…”