Cache Accurate Time Skewing in Iterative Stencil Computations

Abstract

Abstract-We present a time skewing algorithm that breaks the memory wall for certain iterative stencil computations. A stencil computation, even with constant weights, is a completely memory-bound algorithm. For example, for a large 3D domain of 500 3 doubles and 100 iterations on a quad-core Xeon X5482 3.2GHz system, a hand-vectorized and parallelized naive 7-point stencil implementation achieves only 1.4 GFLOPS because the system memory bandwidth limits the performance. Although many efforts have been undertaken to improve the performance of such nested loops, for large data sets they still lag far behind synthetic benchmark performance. The state-of-art automatic locality optimizer PluTo [1] achieves 3.7 GFLOPS for the above stencil, whereas a parallel benchmark executing the inner stencil computation directly on registers performs at 25.1 GFLOPS. In comparison, our algorithm achieves 13.0 GFLOPS (52% of the stencil peak benchmark).We present results for 2D and 3D domains in double precision including problems with gigabyte large data sets. The results are compared against hand-optimized naive schemes, PluTo, the stencil peak benchmark and results from literature. For constant stencils of slope one we break the dependence on the low system bandwidth and achieve at least 50% of the stencil peak, thus performing within a factor two of an ideal system with infinite bandwidth (the benchmark runs on registers without memory access). For large stencils and banded matrices the additional data transfers let the limitations of the system bandwidth come into play again, however, our algorithm still gains a large improvement over the other schemes.

Towards Fast Reverse Time Migration Kernels using Multi-threaded Wavefront Diamond Tiling

“…Figure 2a shows three perspectives of our space-time block diamond tile. It is similar to the work of (Strzodka et al 2011), except we use multi-threaded wavefronts instead of a single-thread wavefront. We utilize an auto-tuning strategy to select the most performance-efficient diamond tile size.…”

Wave equation based stencil optimizations on multi-core CPU

“…Most of previous literature on stencil optimization work only on very low-order (=2) stencils [Datta et al, 2008, Datta, 2009, Nguyen et al, 2010, Henretty et al, 2011, Strzodka et al, 2011, Zumbusch, 2012, Wonnacott and Strout, 2012. These strategies may not work e↵ectively for high-order(=16 or more) stencils, or even the low-order(=4) stencils.…”

“…The CATS algorithm [Strzodka et al, 2011] (time-skewing with diamond spatial block scheme) demonstrated that on a quad-core 3.2GHz Xeon X5482, the GFLOPs/sec dropped by 2.8x when the order of a 3D stencil increased from 2 to 6. Zumbusch [Zumbusch, 2013] also observed the performance dropped by 3x on a single-core Sandy Bridge Intel i7-2600 when the order of a 3D stencil increased from 2 to 12.…”

“…Most of the literatures on stencil vectorization use SIMD intrinsics [Datta et al, 2008, Datta, 2009, Dursun et al, 2009, Henretty et al, 2011, Strzodka et al, 2011, Dursun et al, 2012, Zumbusch, 2012, Zumbusch, 2013, and [Datta et al, 2008, Dursun et al, 2012 explicitly claimed that their compilers had failed to auto-vectorize the stencil codes. Borges [Borges, 2011] gives an example of auto-vectorizing an 8th order stencil kernel, however their procedures only work for stencils of a fixed order because all the finite di↵erence terms are explicitly written in their scheme, so whenever the stencil order changes, the codes need to be rewritten.…”

The Relation Between Diamond Tiling and Hexagonal Tiling

“…Henretty et al [11] use a DSL-based approach relying on different versions of split tiling in combined with a data layout transformation to generate efficient SIMD CPU code. Strzodka [22] uses an in-tile wavefront traversal technique to achieve efficient cache use even with tile sizes larger than the available cache memory. All these approaches generate ef-ficient CPU code.…”