Cache decay: exploiting generational behavior to reduce cache leakage power

Kaxiras, Stefanos; Hu, Zhigang; Martonosi, Margaret

doi:10.1109/isca.2001.937453

Cited by 413 publications

(540 citation statements)

References 29 publications

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“…Cache decay was initially proposed to reduce leakage power in caches [18]. It is based on the generational behavior of cachelines, whereupon a cacheline initially goes through a "live time", where it is accessed frequently, followed by a "dead time", where it simply awaits eviction.…”

Section: Way-selectionmentioning

confidence: 99%

“…We consider the extra dynamic power of decay-induced misses (extra accesses to lower level caches due to incorrect decay of cachelines) to be part of the leakage savings [18]. Having a decaying cache to reduce leakage, one would have to pay for this dynamic-power penalty regardless of any additional mechanism for dynamic power reduction.…”

Section: Power Issuesmentioning

confidence: 99%

“…We propose a new approach for reducing dynamic power in set-associative caches by exploiting a previous leakage-saving proposal. Specifically, we use Cache Decay [18] to identify dead cachelines, which we then exclude from the associative search. Our proposal is different from wayprediction proposals that precede it.…”

mentioning

confidence: 99%

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Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Κεραμίδας

Xekalakis

2009

Transactions on High-Performance Embedded Architectures and Compilers II

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Abstract. In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and leakage management in the same framework. The main intuition is that in a decaying cache, dead lines in a set need not be searched. Thus, rather than trying to predict which cache way holds a specific line, we predict, for each way, whether the line could be live in it. We access all the ways that possibly contain the live line and we call this way selection. In contrast to way-prediction, way-selection cannot be wrong: the line is either in the selected ways or not in the cache. The important implication is that we have a fixed hit time -indispensable for both performance and ease-of-implementation reasons. One would expect way-selection to be inferior to sophisticated way-prediction in terms of the total ways accessed, but in fact it can even do better. To achieve this level of accuracy we use Decaying Bloom filters to track only the live lines in ways -dead lines are automatically purged. We offer efficient implementations of such autonomously Decaying Bloom filters, using novel quasi-static cells. Our prediction approach affords us high-accuracy in narrowing the choice of ways for hits as well as the ability to predict misses -a known weakness of way-prediction -thus outperforming sophisticated way-prediction. Furthermore, our approach scales significantly better than way-prediction to higher associativity. We show that decay is a necessary component in this approach -way-selection and Bloom filters alone cannot compete with sophisticated way-prediction. We compare our approach to Multi-MRU and we show that without even considering leakage savings -we surpass it terms of relative power savings and in relative energy-delay in 4-way (9%) and more so in 8-way (20%) and 16-way caches (31%).

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Section: Way-selectionmentioning

confidence: 99%

Section: Power Issuesmentioning

confidence: 99%

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Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Κεραμίδας

Xekalakis

2009

Transactions on High-Performance Embedded Architectures and Compilers II

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“…For shared caches, different data retention policies can be applied to different processes in order to maximize the use of the shared capacity [17]. Other approaches like cache decay can target the same types of data in order to reduce the used capacity in a cache by turning off lines that have remained idle for long periods of time [18].…”

Section: A Cache Design and Managementmentioning

confidence: 99%

“…Figure 7 shows the average number of times the different groups of data blocks remain unaccessed for more than one million cycles. (We choose this time frame to designate idleness based on [18] which showed that it might be worthwhile to decay cache lines in a level two cache if they remained idle for more than one million cycles.) Data that goes idle multiple times is data that is used cyclically throughout its lifetime, going idle for the period of time between uses.…”

Section: Data Reusementioning

confidence: 99%

Understanding the applicability of CMP performance optimizations on data mining applications

Jibaja

Shaw

2009

2009 IEEE International Symposium on Workload Characterization (IISWC)

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Abstract-A major challenge to the creation of chip multiprocessors is designing the on-chip memory and communication resources to efficiently support parallel workloads. A variety of cache organizations, data management techniques, and hardware optimizations that take advantage of specific data characteristics have been developed to improve application performance. The success of these approaches depends on applications exhibiting the presumed data characteristics.Data mining applications are a growing class of applications that discover patterns in large sets of collected data. Because these applications tend to be highly parallelizable, they represent an important workload for chip multiprocessors. However, the memory intensive nature of these applications means that they will stress these chips' memory and communication resources.In this paper, we examine the data usage characteristics of a set of parallel data mining applications to determine the applicability of existing chip multiprocessor approaches to these applications. We show diversity of characteristics across and within these applications, making some techniques more applicable than others. We also discuss software approaches that could be used to either provide information to the hardware or assist the hardware in dynamically discovering data characteristics needed for the deployment of these techniques.

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Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors

You

Lee

2005

Languages and Compilers for Parallel Computing

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Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts also indicate architecture, compiler, and software participations can help reduce the switching activities (also known as dynamic power) on microprocessors. This raises interests on the issues to employ architecture and compiler efforts to reduce leakage power (also known as static power) on microprocessors. In this paper, we investigate the compiler analysis techniques related to reducing leakage power. The architecture model in our design is a system with an instruction set to support the control of power gating in the component levels. Our compiler gives an analysis framework to utilize the instruction to reduce the leakage power. We present a data flow analysis framework to estimate the component activities at fixed points of programs with the consideration of pipelines of architectures. We also give the equation for the compiler to decide if the employment of the power gating instructions on given program blocks will benefit the total energy reductions. As the duration of power gating on components on given program routines is related to program branches, we propose a set of scheduling policy include Basic Blk Sched, MIN Path Sched, and AVG Path Sched mechanisms and evaluate the effectiveness of those schemes. Our experiment is done by incorporating our compiler analysis and scheduling policy into SUIF compiler tools [32] and by simulating the energy consumptions on Wattch toolkits [6]. Experimental results show our mechanisms are effective in reducing leakage powers on microprocessors.

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Cache decay: exploiting generational behavior to reduce cache leakage power

Abstract: Power dissipation is increasingly important in CPUs rang

Cited by 413 publications

References 29 publications

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Understanding the applicability of CMP performance optimizations on data mining applications

Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors

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