Cache-Oblivious Hashing

Pagh, Rasmus; Wei, Zhewei; Yi, Ke; Zhang, Qin

doi:10.1007/s00453-013-9763-6

Cited by 11 publications

(12 citation statements)

References 26 publications

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“…MemC3 [8] not only ensured the high space utilization but also eliminated the limitation of the hash table size through labeling and an optimized locking mechanism. Hopscotch hashing [14] and Cache-oblivious hashing [15] improved the throughput performance by increasing the index pointer space to ensure access concurrency. Li et al [31] achieved the high concurrency of access through Hardware Transaction Memory (HTM) and a coarse locking mechanism.…”

Section: Related Workmentioning

confidence: 99%

“…Li et al [31] achieved the high concurrency of access through Hardware Transaction Memory (HTM) and a coarse locking mechanism. FlashStore [15] mapped an object to 16 bucket positions with Cuckoo hash, and increased the probability of looking for a free slot when inserting the object. Kirsch et al [16] used additional hidden space to reduce the overhead of looking for free space.…”

Section: Related Workmentioning

confidence: 99%

“…In a recent work on hash tables, the Cuckoo Hash Table (CHT) [9] has been proposed; it is based on the cuckoo algorithm and it maps the original single data into multiple buckets. CHT replaces the mapping and the linked list operations of the traditional hash tables and has the characteristics of fast access and saving space, which has been widely applied and studied in the hash table management [10][11][12] and data storage systems [4,8,[13][14][15][16] .…”

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confidence: 99%

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Hybrid Access Cache Indexing Framework Adapted to GPU

Zhang¹,

Zhang²,

Wu³

et al. 2021

International Journal of Software and Informatics

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Hash tables, as a type of data indexing structure that provides efficient data access based on key values, are widely used in various computer applications, especially in system software, databases, and high-performance computing field that requires extremely high performance. In network, cloud computing and IoT services, hash tables have become the core system components of cache systems. However, with the large-scale increase in the amount of large-scale data, performance bottlenecks have gradually emerged in systems designed with a multi-core CPU as the core of the hash table structure. There is an urgent need to further improve the high performance and scalability of the hash tables. With the increasing popularity of general-purpose Graphic Processing Units (GPUs) and the substantial improvement of hardware computing capabilities and concurrency performance, various types of system software tasks with parallel computing as the core have been optimized on the GPU and have achieved considerable performance improvements. Due to the sparseness and randomness, using the existing parallel structure of the hash tables directly on the GPUs will inevitably bring high-frequency memory access and frequent bus data transmission, which affects the performance of the hash tables on the GPUs. This study focuses on the analysis of memory access, hit ratio, and index overhead of hash table indexes in the cache system. The hybrid access cache indexing framework CCHT (Cache Cuckoo Hash Table ) adapted to GPU is proposed and provided. The cache strategy suitable to different requirements of hit ratios and index overheads allows concurrent execution of write and query operations, maximizing the use of the computing performance and concurrency characteristics of GPU hardware, reducing memory access and bus transferring overhead. Through GPU hardware implementation and experimental verification, CCHT is shown to have better performance than other cache indexing hash tables while ensuring cache hit ratios.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

mentioning

confidence: 99%

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Hybrid Access Cache Indexing Framework Adapted to GPU

Zhang¹,

Zhang²,

Wu³

et al. 2021

International Journal of Software and Informatics

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“…The competition between the two technology routes has intensified in recent years, from the basic CPU platform [92] to the NUMA platform [93], and it will certainly be extended to the new processor platforms in the future. The underlying reason behind this phenomenon is that it is difficult to quantify the optimization techniques, as in the field of in-memory database technology, although there are numerous hash structures and join algorithms currently [94][95][96], the simple question of which is the best in-memory hash join algorithm is still unknown [97]. In the future, when the new hardware environment is more and more complicated, performance should not be the only indicator to evaluate the advantages and disadvantages of algorithm.…”

Section: Query Processing and Optimization In Platforms With New Hardmentioning

confidence: 99%

The New Hardware Development Trend and the Challenges in Data Management and Analysis

Pan

Zhang

et al. 2018

Data Sci. Eng.

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Hardware techniques and environments underwent significant transformations in the field of information technology, represented by high-performance processors and hardware accelerators characterized by abundant heterogeneous parallelism, nonvolatile memory with hybrid storage hierarchies, and RDMA-enabled high-speed network. Recent hardware trends in these areas deeply affect data management and analysis applications. In this paper, we first introduce the development trend of the new hardware in computation, storage, and network dimensions. Then, the related research techniques which affect the upper data management system design are reviewed. Finally, challenges and opportunities are addressed for the key technologies of data management and analysis in new hardware environments.

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“…We note that cache-oblivious data structures are not limited to search trees. They have been proposed in a variety of settings, some of which include hash tables [9], meshes [10], [11], and Bloom filters [12].…”

Section: Introductionmentioning

confidence: 99%

Optimal hierarchical layouts for cache-oblivious search trees

Lindström

Rajan

2014

2014 IEEE 30th International Conference on Data Engineering

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This paper proposes a general framework for generating cache-oblivious layouts for binary search trees. A cache-oblivious layout attempts to minimize cache misses on any hierarchical memory, independent of the number of memory levels and attributes at each level such as cache size, line size, and replacement policy. Recursively partitioning a tree into contiguous subtrees and prescribing an ordering amongst the subtrees, Hierarchical Layouts generalize many commonly used layouts for trees such as in-order, pre-order and breadthfirst. They also generalize the various flavors of the van Emde Boas layout, which have previously been used as cache-oblivious layouts. Hierarchical Layouts thus unify previous attempts at deriving layouts for search trees.The paper then derives a new locality measure (the Weighted Edge Product) that mimics the probability of cache misses at multiple levels, and shows that layouts that reduce this measure perform better. We analyze the various degrees of freedom in the construction of Hierarchical Layouts, and investigate the relative effect of each of these decisions in the construction of cacheoblivious layouts. Optimizing the Weighted Edge Product for complete binary search trees, we introduce the MINWEP layout, and show that it outperforms previously used cache-oblivious layouts by almost 20%.

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Cache-Oblivious Hashing

Cited by 11 publications

References 26 publications

Hybrid Access Cache Indexing Framework Adapted to GPU

Hybrid Access Cache Indexing Framework Adapted to GPU

The New Hardware Development Trend and the Challenges in Data Management and Analysis

Optimal hierarchical layouts for cache-oblivious search trees

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