CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

Abstract

Stressors have been used since 90 nm technology to improve device performance to overcome the limitations of scaling. The stressors, including, -CPEN, TPEN, SMT, and e-SiGe to improve NMOS and PMOS drive current exhibit proximity dependence. In addition, unintentional stressors such as STI edge proximity introduce additional layout dependencies. Two devices with the same L and W can have significantly different drive strength depending on their surroundings. There have been limited studies to optimize the design layout to reduce the layout-dependent stress degradation. Circuit and layout designers have few tools they can use to quickly and effectively optimize the layout to reduce device degradation due to layoutdependent stress effects. In this paper, we present a comprehensive set of CAD utilities, and stress-related layout guidelines to optimize the layout for full custom macros to reduce the layout-dependent stress effects prior to doing full timing characterization, including stress effects.

Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs

“…While [8] has contributed to this domain for stress in 45 nm technology, a faster methodology which can target 28 nm, and also include lithographic effects is needed. In this paper, we target this particular gap.…”