Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors

Sivonen, P.; Vilander, A.; Pärssinen, Aarno

doi:10.1109/tcsi.2004.841571

Cited by 23 publications

(8 citation statements)

References 24 publications

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“… Literature survey of up-conversion mixers [ 14 , 22 , 31 , 33 , 36 , 37 , 38 , 39 , 40 , 41 ] with operating frequencies of 15–35 GHz. ( a ) Conversion gain, ( b ) OP 1 dB.…”

Section: Figurementioning

confidence: 99%

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Siddique

Delwar

Behera

et al. 2021

Sensors

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A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm2.

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“… Literature survey of up-conversion mixers [ 14 , 22 , 31 , 33 , 36 , 37 , 38 , 39 , 40 , 41 ] with operating frequencies of 15–35 GHz. ( a ) Conversion gain, ( b ) OP 1 dB.…”

Section: Figurementioning

confidence: 99%

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Siddique

Delwar

Behera

et al. 2021

Sensors

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“…The supply voltage is only 750 mV and the IM2-performance is still very good. A technique for canceling IM 2 in the transconductance stage of an active mixer is presented in [20]. A digital technique for tuning of the mixer core is provided in [21].…”

Section: Previous Ip 2 Enhancement Techniquesmentioning

confidence: 99%

A BiCMOS single ended multiband RF-amplifier and mixer with DC-offset and second order distortion suppression

Tired

2011

Analog Integr Circ Sig Process

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Direct conversion receivers are widely used for full duplex mobile radio communication systems. This paper describes a novel SAW-less single-ended RF amplifier connected to a single-ended mixer with a feedback loop that suppresses the second-order distortion from TX cross modulation of the LO-leakage as well as DCoffset at the mixer output. In Monte Carlo simulations the design achieves ?47 dBm minimum IIP 2 with 32 dB conversion voltage gain. The advantage with the proposed architecture is that it is fully single-ended. Especially in multiband integrated radios this is highly desirable since the pin-count for the LNAs is reduced by half. The PCB routing of the RF input signal is simplified. The design requires two off-chip filter capacitors of non critical value intended to be placed on the laminate inside the package.

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“…Third-order linearization approaches include cancellation of non-linearities in digital front-end [29], locally at RF [2], [28], [30] or using alternate path to process third-order components [31]. Similarly, second-order linearization can be divided into robust local linearity boosting techniques [32], [33] as well as to different calibration schemes [11], [34]. This can be interpreted that to be competitive receiver architecture must either provide inherently highly linear structure against out-of-band interferers or means to calibrate or cancel out any large interferer or resulted non-linearity product over a wide band of possible frequencies.…”

Section: A Receiver Architectures For Portable Devicesmentioning

confidence: 99%

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

Koli

Kallioinen

Jussila

et al. 2010

IEEE J. Solid-State Circuits

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Direct delta-sigma receiver architecture is introduced for wireless communication systems, such as LTE or WiMax. Architecture is based on direct downconversion, delta-sigma feedback that is up-converted to RF, and N-path filtering technique. Hence, the core receiver functions including channel selection filtering are embedded to a RF ADC with excellent linearity performance. This is achieved by transforming narrow-band filtering partially to RF injecting feedback into the input of the second amplifier stage, hence relieving requirements of the most critical subsequent stages. A 900-MHz direct delta-sigma receiver prototype occupies an active area of 1 2 mm 2 in 65-nm CMOS. The receiver for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and delta-sigma modes, respectively, and out-of-band IIP3 up to +4 dBm when the delta-sigma loop is active. The chip consumes 80 mW from a 1.2-V supply.

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Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors

Cited by 23 publications

References 24 publications

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

A BiCMOS single ended multiband RF-amplifier and mixer with DC-offset and second order distortion suppression

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

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