CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

Enokimoto, K.; Wen, Xiaoqing; Yamato, Yuta; Miyase, Kohei; Sone, H.; Kajihara, Seiji; Aso, Masao; Furukawa, Hiroshi

doi:10.1109/ats.2009.22

Cited by 12 publications

(20 citation statements)

References 21 publications

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“…Methods [7][8][9][10][11][12][13] attempt to reduce the total amount of switching activity for all logic gates in a circuit. Methods [14][15][16] extract paths that are strongly related to overtesting, and then reduce the switching activity around those paths so that excessive delay on these paths can be suppressed.…”

Section: Introductionmentioning

confidence: 99%

“…In at-speed testing, excessive power in testing causes overtesting for a circuit produced with nanoscale technologies [7][8][9][10][11][12][13][14][15][16]. Obviously, such additional constraints increase the computation time of test generation.…”

Section: Introductionmentioning

confidence: 99%

“…Low-power test generation techniques have been proposed in order to reduce power consumption caused by testing [7][8][9][10][11][12][13][14][15][16]. Low-power test generation controls logic values so as to minimize the amount of switching activity caused by applying test vectors.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Search Space Reduction for Low-Power Test Generation

Miyase

Sauer

Becker

et al. 2013

2013 22nd Asian Test Symposium

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Ongoing research to shrink feature sizes of LSI circuits leads to an always increasing number of logic gates in a circuit. In general, the complexity of test generation depends on the size of a circuit. Furthermore, modern test generation methods have to consider power reduction in addition to fault detection, since excessive power caused by testing may result in overtesting. In this work, we propose a method to reduce the computation time of low-power test generation. The proposed method specifies gates which will cause power issues, consequently reducing the search space for X-filling technique. The reduction of search space for Xfilling also further minimizes the amount of switching activity. Experimental results for circuits of OpenCores provided by IWLS2005 benchmarks show that the proposed method achieves both a reduced computation time and at the same time increased power reduction compared to previous methods.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Search Space Reduction for Low-Power Test Generation

Miyase

Sauer

Becker

et al. 2013

2013 22nd Asian Test Symposium

View full text Add to dashboard Cite

show abstract

“…The reduction of capture power in critical areas is considered in [5], [15], [16]. Additionally, layout-aware techniques were proposed to increase the accuracy of the switching activity estimation targeting critical areas [17], [18].…”

Section: Introductionmentioning

confidence: 99%

Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill

Eggersglüß

2013

2013 22nd Asian Test Symposium

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Abstract-Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel X-filling technique Opt-Justification-fill which uses optimization techniques to compute promising Xbits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increases only moderately which leads to reduced test costs.

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“…The reduction of capture power in critical areas is considered in [9,32,35,37]. Additionally, layout-aware techniques were proposed to increase the accuracy of the switching activity estimation targeting critical areas [18,19].…”

mentioning

confidence: 99%

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Eggersglüβ

2014

J Electron Test

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Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic Xfilling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.

show abstract

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

Cited by 12 publications

References 21 publications

Search Space Reduction for Low-Power Test Generation

Search Space Reduction for Low-Power Test Generation

Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

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