2003
DOI: 10.1049/el:20031046
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CCII-based floating inductance simulator with compensated series resistance

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Cited by 68 publications
(38 citation statements)
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“…10. It is confirmed that the cut-off frequency can be adjusted by equivalent inductance by means of input bias current as shown in (6). …”
Section: Simulation Resultssupporting
confidence: 55%
“…10. It is confirmed that the cut-off frequency can be adjusted by equivalent inductance by means of input bias current as shown in (6). …”
Section: Simulation Resultssupporting
confidence: 55%
“…However, to implement spiral inductors in integrated circuits is still a problem because of their disadvantageous in the usage of space, weight, cost and tunability. Therefore, many lossless positive grounded simulated inductors [3][4][5][6][7][8][9][10][11] and floating positive inductor simulators [12][13] were previously presented, Mohan design a lossless floating inductance in 1998 [3], however he uses two dual output CCIIs, two resistors, and one grounded capacitor. And the circuit introduced in [3][4][5][6] lack of electronic tenability, or excessive use of active and/or passive elements.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, many lossless positive grounded simulated inductors [3][4][5][6][7][8][9][10][11] and floating positive inductor simulators [12][13] were previously presented, Mohan design a lossless floating inductance in 1998 [3], however he uses two dual output CCIIs, two resistors, and one grounded capacitor. And the circuit introduced in [3][4][5][6] lack of electronic tenability, or excessive use of active and/or passive elements. The circuits of [7][8][9][10][11] use a minimum number of active and passive components without requiring passive component matching constraints.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, parasitic impedance effect reduction methods have been developed in the literature to reduce the X terminal parasitic resistance effects and to increase the high frequency performance of the circuits [5,16,20,30]. Further, a method was proposed in [9] to reduce the effects of the Z terminal parasitic resistance of the current conveyor and to increase the low frequency performance of the floating inductor simulator given in [13]. Similarly, a method to increase the low frequency performance of the grounded inductor simulators was developed in [31].…”
mentioning
confidence: 99%
“…Similarly, a method to increase the low frequency performance of the grounded inductor simulators was developed in [31]. The method used in [9] and [31] brings extra CCII(s) to the input port(s) of the inductor simulators to accomplish parasitic impedance effect reduction. However, neither of the methods presented in [9] and [31] can be applied to the other circuits employing active devices with Z and Y terminal parasitic resistances.…”
mentioning
confidence: 99%